serialport.tan.qmsg

VHDL基础的编程源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register counter_out:inst\|lpm_counter:counter_rtl_0\|dffs\[0\] register serialport_tx:inst7\|idata\[0\] 47.17 MHz 21.2 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 47.17 MHz between source register \"counter_out:inst\|lpm_counter:counter_rtl_0\|dffs\[0\]\" and destination register \"serialport_tx:inst7\|idata\[0\]\" (period= 21.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.800 ns + Longest register register " "Info: + Longest register to register delay is 12.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter_out:inst\|lpm_counter:counter_rtl_0\|dffs\[0\] 1 REG LC48 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC48; Fanout = 11; REG Node = 'counter_out:inst\|lpm_counter:counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 7.100 ns bcd_ascii:inst2\|Mux~330 2 COMB LC94 2 " "Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 7.100 ns; Loc. = LC94; Fanout = 2; COMB Node = 'bcd_ascii:inst2\|Mux~330'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "7.100 ns" { counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] bcd_ascii:inst2|Mux~330 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 12.800 ns serialport_tx:inst7\|idata\[0\] 3 REG LC15 4 " "Info: 3: + IC(2.600 ns) + CELL(3.100 ns) = 12.800 ns; Loc. = LC15; Fanout = 4; REG Node = 'serialport_tx:inst7\|idata\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.700 ns" { bcd_ascii:inst2|Mux~330 serialport_tx:inst7|idata[0] } "NODE_NAME" } "" } } { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 58.59 % ) " "Info: Total cell delay = 7.500 ns ( 58.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.300 ns ( 41.41 % ) " "Info: Total interconnect delay = 5.300 ns ( 41.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "12.800 ns" { counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] bcd_ascii:inst2|Mux~330 serialport_tx:inst7|idata[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "12.800 ns" { counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] bcd_ascii:inst2|Mux~330 serialport_tx:inst7|idata[0] } { 0.000ns 2.700ns 2.600ns } { 0.000ns 4.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.700 ns - Smallest " "Info: - Smallest clock skew is 6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 48 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 48; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 136 256 424 152 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns baud_div:inst5\|baudrate_clock 2 REG LC51 18 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC51; Fanout = 18; REG Node = 'baud_div:inst5\|baudrate_clock'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "2.500 ns" { clock_24M baud_div:inst5|baudrate_clock } "NODE_NAME" } "" } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns serialport_tx:inst7\|idata\[0\] 3 REG LC15 4 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC15; Fanout = 4; REG Node = 'serialport_tx:inst7\|idata\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.100 ns" { baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[0] } "NODE_NAME" } "" } } { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 71.29 % ) " "Info: Total cell delay = 7.200 ns ( 71.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 28.71 % ) " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "10.100 ns" { clock_24M baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 48 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 48; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 136 256 424 152 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter_out:inst\|lpm_counter:counter_rtl_0\|dffs\[0\] 2 REG LC48 11 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC48; Fanout = 11; REG Node = 'counter_out:inst\|lpm_counter:counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "0.900 ns" { clock_24M counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "10.100 ns" { clock_24M baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "12.800 ns" { counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] bcd_ascii:inst2|Mux~330 serialport_tx:inst7|idata[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "12.800 ns" { counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] bcd_ascii:inst2|Mux~330 serialport_tx:inst7|idata[0] } { 0.000ns 2.700ns 2.600ns } { 0.000ns 4.400ns 3.100ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "10.100 ns" { clock_24M baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter_out:inst|lpm_counter:counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock_24M 42 " "Warning: Circuit may not operate. Detected 42 non-operational path(s) clocked by clock \"clock_24M\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "counter_out:inst\|carrier pwm:inst1\|lpm_counter:delay_counter_rtl_1\|dffs\[1\] clock_24M 7.1 ns " "Info: Found hold time violation between source  pin or register \"counter_out:inst\|carrier\" and destination pin or register \"pwm:inst1\|lpm_counter:delay_counter_rtl_1\|dffs\[1\]\" for clock \"clock_24M\" (Hold time is 7.1 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "13.300 ns + Largest " "Info: + Largest clock skew is 13.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 16.700 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 16.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 48 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 48; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 136 256 424 152 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns baud_div:inst5\|baudrate_clock 2 REG LC51 18 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC51; Fanout = 18; REG Node = 'baud_div:inst5\|baudrate_clock'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "2.500 ns" { clock_24M baud_div:inst5|baudrate_clock } "NODE_NAME" } "" } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.800 ns) 11.700 ns counter:inst3\|carrier 3 REG LC80 34 " "Info: 3: + IC(2.900 ns) + CELL(3.800 ns) = 11.700 ns; Loc. = LC80; Fanout = 34; REG Node = 'counter:inst3\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "6.700 ns" { baud_div:inst5|baudrate_clock counter:inst3|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 16.700 ns pwm:inst1\|lpm_counter:delay_counter_rtl_1\|dffs\[1\] 4 REG LC38 34 " "Info: 4: + IC(2.800 ns) + CELL(2.200 ns) = 16.700 ns; Loc. = LC38; Fanout = 34; REG Node = 'pwm:inst1\|lpm_counter:delay_counter_rtl_1\|dffs\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.000 ns" { counter:inst3|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 65.87 % ) " "Info: Total cell delay = 11.000 ns ( 65.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns ( 34.13 % ) " "Info: Total interconnect delay = 5.700 ns ( 34.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "16.700 ns" { clock_24M baud_div:inst5|baudrate_clock counter:inst3|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.700 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock counter:inst3|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 2.900ns 2.800ns } { 0.000ns 2.500ns 2.500ns 3.800ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 48 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 48; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 136 256 424 152 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter_out:inst\|carrier 2 REG LC36 69 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC36; Fanout = 69; REG Node = 'counter_out:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "0.900 ns" { clock_24M counter_out:inst|carrier } "NODE_NAME" } "" } } { "counter_out.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M counter_out:inst|carrier } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter_out:inst|carrier } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "16.700 ns" { clock_24M baud_div:inst5|baudrate_clock counter:inst3|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.700 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock counter:inst3|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 2.900ns 2.800ns } { 0.000ns 2.500ns 2.500ns 3.800ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M counter_out:inst|carrier } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter_out:inst|carrier } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } { { "counter_out.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns - Shortest register register " "Info: - Shortest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter_out:inst\|carrier 1 REG LC36 69 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 69; REG Node = 'counter_out:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { counter_out:inst|carrier } "NODE_NAME" } "" } } { "counter_out.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.100 ns) 5.900 ns pwm:inst1\|lpm_counter:delay_counter_rtl_1\|dffs\[1\] 2 REG LC38 34 " "Info: 2: + IC(2.800 ns) + CELL(3.100 ns) = 5.900 ns; Loc. = LC38; Fanout = 34; REG Node = 'pwm:inst1\|lpm_counter:delay_counter_rtl_1\|dffs\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.900 ns" { counter_out:inst|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 52.54 % ) " "Info: Total cell delay = 3.100 ns ( 52.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 47.46 % ) " "Info: Total interconnect delay = 2.800 ns ( 47.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.900 ns" { counter_out:inst|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.900 ns" { counter_out:inst|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } { 0.000ns 2.800ns } { 0.000ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "counter_out.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 48 -1 0 } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "16.700 ns" { clock_24M baud_div:inst5|baudrate_clock counter:inst3|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.700 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock counter:inst3|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 2.900ns 2.800ns } { 0.000ns 2.500ns 2.500ns 3.800ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M counter_out:inst|carrier } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter_out:inst|carrier } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.900 ns" { counter_out:inst|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.900 ns" { counter_out:inst|carrier pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1] } { 0.000ns 2.800ns } { 0.000ns 3.100ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "baud_div:inst5\|lpm_counter:delay_counter_rtl_2\|dffs\[17\] baudrate\[1\] clock_24M 15.500 ns register " "Info: tsu for register \"baud_div:inst5\|lpm_counter:delay_counter_rtl_2\|dffs\[17\]\" (data pin = \"baudrate\[1\]\", clock pin = \"clock_24M\") is 15.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest pin register " "Info: + Longest pin to register delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns baudrate\[1\] 1 PIN PIN_81 28 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_81; Fanout = 28; PIN Node = 'baudrate\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { baudrate[1] } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 456 256 424 472 "baudrate\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.300 ns) 5.300 ns rtl~410 2 COMB LC52 1 " "Info: 2: + IC(2.600 ns) + CELL(1.300 ns) = 5.300 ns; Loc. = LC52; Fanout = 1; COMB Node = 'rtl~410'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.900 ns" { baudrate[1] rtl~410 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 6.200 ns rtl~415 3 COMB LC53 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 6.200 ns; Loc. = LC53; Fanout = 1; COMB Node = 'rtl~415'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "0.900 ns" { rtl~410 rtl~415 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 10.200 ns rtl~407 4 COMB LC54 35 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 10.200 ns; Loc. = LC54; Fanout = 35; COMB Node = 'rtl~407'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "4.000 ns" { rtl~415 rtl~407 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 16.000 ns baud_div:inst5\|lpm_counter:delay_counter_rtl_2\|dffs\[17\] 5 REG LC64 30 " "Info: 5: + IC(2.700 ns) + CELL(3.100 ns) = 16.000 ns; Loc. = LC64; Fanout = 30; REG Node = 'baud_div:inst5\|lpm_counter:delay_counter_rtl_2\|dffs\[17\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.800 ns" { rtl~407 baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.700 ns ( 66.88 % ) " "Info: Total cell delay = 10.700 ns ( 66.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.300 ns ( 33.13 % ) " "Info: Total interconnect delay = 5.300 ns ( 33.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "16.000 ns" { baudrate[1] rtl~410 rtl~415 rtl~407 baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.000 ns" { baudrate[1] baudrate[1]~out rtl~410 rtl~415 rtl~407 baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } { 0.000ns 0.000ns 2.600ns 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 1.300ns 0.900ns 4.000ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 48 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 48; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 136 256 424 152 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns baud_div:inst5\|lpm_counter:delay_counter_rtl_2\|dffs\[17\] 2 REG LC64 30 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC64; Fanout = 30; REG Node = 'baud_div:inst5\|lpm_counter:delay_counter_rtl_2\|dffs\[17\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "0.900 ns" { clock_24M baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "16.000 ns" { baudrate[1] rtl~410 rtl~415 rtl~407 baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.000 ns" { baudrate[1] baudrate[1]~out rtl~410 rtl~415 rtl~407 baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } { 0.000ns 0.000ns 2.600ns 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 1.300ns 0.900ns 4.000ns 3.100ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "3.400 ns" { clock_24M baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out baud_div:inst5|lpm_counter:delay_counter_rtl_2|dffs[17] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}