serialport.map.rpt

VHDL基础的编程源代码

; CBXI_PARAMETER         ; NOTHING           ; Untyped                                            ;
+------------------------+-------------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: baud_div:inst5|lpm_add_sub:add_rtl_3 ;
+------------------------+-------------+------------------------------------------------+
; Parameter Name         ; Value       ; Type                                           ;
+------------------------+-------------+------------------------------------------------+
; LPM_WIDTH              ; 14          ; Untyped                                        ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                        ;
; LPM_DIRECTION          ; ADD         ; Untyped                                        ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                        ;
; LPM_PIPELINE           ; 0           ; Untyped                                        ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                        ;
; REGISTERED_AT_END      ; 0           ; Untyped                                        ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                        ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                        ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                        ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                             ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                                        ;
; USE_WYS                ; OFF         ; Untyped                                        ;
; STYLE                  ; FAST        ; Untyped                                        ;
; CBXI_PARAMETER         ; add_sub_pdh ; Untyped                                        ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                   ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                 ;
+------------------------+-------------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter_out:inst|lpm_add_sub:add_rtl_4 ;
+------------------------+-------------+--------------------------------------------------+
; Parameter Name         ; Value       ; Type                                             ;
+------------------------+-------------+--------------------------------------------------+
; LPM_WIDTH              ; 24          ; Untyped                                          ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                          ;
; LPM_DIRECTION          ; ADD         ; Untyped                                          ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                          ;
; LPM_PIPELINE           ; 0           ; Untyped                                          ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                          ;
; REGISTERED_AT_END      ; 0           ; Untyped                                          ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                          ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                          ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                          ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                               ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                                          ;
; USE_WYS                ; OFF         ; Untyped                                          ;
; STYLE                  ; FAST        ; Untyped                                          ;
; CBXI_PARAMETER         ; add_sub_joh ; Untyped                                          ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                       ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                     ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                     ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                   ;
+------------------------+-------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/03-源码文件/VHDL/07-串口发送/serialport.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 25 20:08:21 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serialport -c serialport
Info: Found 2 design units, including 1 entities, in source file baud_div.vhd
    Info: Found design unit 1: baud_div-baud_div_architecture
    Info: Found entity 1: baud_div
Info: Found 2 design units, including 1 entities, in source file bcd_ascii.vhd
    Info: Found design unit 1: bcd_ascii-bcd_ascii_architecture
    Info: Found entity 1: bcd_ascii
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-counter_architecture
    Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file pwm.vhd
    Info: Found design unit 1: pwm-pwm_architecture
    Info: Found entity 1: pwm
Info: Found 1 design units, including 1 entities, in source file serialport.bdf
    Info: Found entity 1: serialport
Info: Found 2 design units, including 1 entities, in source file serialport_tx.vhd
    Info: Found design unit 1: serialport_tx-serialport_tx_architecture
    Info: Found entity 1: serialport_tx
Info: Found 2 design units, including 1 entities, in source file counter_out.vhd
    Info: Found design unit 1: counter_out-counter_out_architecture
    Info: Found entity 1: counter_out
Info: Elaborating entity "serialport" for the top level hierarchy
Warning: Port "carrier" of type counter_out and instance "inst" is missing source signal
Warning: Port "counter" of type counter_out and instance "inst" is missing source signal
Warning: Port "baudrate_clock" of type baud_div and instance "inst5" is missing source signal
Warning: Port "carrier" of type counter and instance "inst3" is missing source signal
Info: Elaborating entity "serialport_tx" for hierarchy "serialport_tx:inst7"
Warning (10036): Verilog HDL or VHDL warning at serialport_tx.vhd(66): object "nextState" assigned a value but never read
Info: Elaborating entity "pwm" for hierarchy "pwm:inst1"
Info: Elaborating entity "counter_out" for hierarchy "counter_out:inst"
Info: Elaborating entity "counter" for hierarchy "counter:inst3"
Info: Elaborating entity "baud_div" for hierarchy "baud_div:inst5"
Warning (10492): VHDL Process Statement warning at baud_div.vhd(51): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "bcd_ascii" for hierarchy "bcd_ascii:inst2"
Info (10425): VHDL Case Statement information at bcd_ascii.vhd(72): OTHERS choice is never selected
Warning: Reduced register "serialport_tx:inst7|idata[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "counter:inst3|delay_counter" with stuck data_in port to stuck value GND
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter_out:inst|counter[0]~16"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "pwm:inst1|delay_counter[0]~64"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=18) from the following logic: "baud_div:inst5|delay_counter[0]~18"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 24 buffer(s)
    Info: Ignored 24 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register "serialport_tx:inst7|idata[5]" merged to single register "serialport_tx:inst7|idata[4]"
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock_24M" to global clock signal
    Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Implemented 145 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 1 output pins
    Info: Implemented 128 macrocells
    Info: Implemented 7 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Sun Mar 25 20:08:39 2007
    Info: Elapsed time: 00:00:18