serialport.sim.rpt

VHDL基础的编程源代码

+------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[1]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[1]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[1]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[2]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[2]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[2]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[2]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[3]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[3]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[3]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[3]          ; dataout          ;
; |serialport|rtl~404                                                    ; |serialport|rtl~404                                                    ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|_~535       ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|_~535       ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[4]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[4]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[4]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[4]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[5]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[5]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[5]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[5]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[6]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[6]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[6]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[6]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[7]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[7]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[7]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[7]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[8]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[8]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[8]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[8]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[9]     ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[9]     ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[9]          ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[9]          ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[10]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[10]    ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[10]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[10]         ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[11]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[11]    ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[11]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[11]         ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[12]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[12]    ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[12]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[12]         ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[13]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[13]    ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[13]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[13]         ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[14]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[14]    ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[14]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[14]         ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[15]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[15]    ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[15]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[15]         ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[16]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[16]    ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[16]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[16]         ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[17]    ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[17]    ; dataout          ;
; |serialport|baud_div:inst5|baudrate_clock                              ; |serialport|baud_div:inst5|baudrate_clock                              ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[17]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[17]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[18]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[18]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[19]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[19]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[20]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[20]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[21]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[21]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[22]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[22]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[23]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[23]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[24]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[24]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[25]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[25]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[26]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[26]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[27]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[27]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[28]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[28]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[29]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[29]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[30]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[30]         ; dataout          ;
; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[31]         ; |serialport|pwm:inst1|lpm_counter:delay_counter_rtl_1|dffs[31]         ; dataout          ;
; |serialport|serialport_tx:inst7|idata[6]                               ; |serialport|serialport_tx:inst7|idata[6]                               ; dataout          ;
; |serialport|serialport_tx:inst7|idata[4]                               ; |serialport|serialport_tx:inst7|idata[4]                               ; dataout          ;
; |serialport|serialport_tx:inst7|idata[3]                               ; |serialport|serialport_tx:inst7|idata[3]                               ; dataout          ;
; |serialport|serialport_tx:inst7|idata[2]                               ; |serialport|serialport_tx:inst7|idata[2]                               ; dataout          ;
; |serialport|serialport_tx:inst7|idata[1]                               ; |serialport|serialport_tx:inst7|idata[1]                               ; dataout          ;
; |serialport|serialport_tx:inst7|idata[0]                               ; |serialport|serialport_tx:inst7|idata[0]                               ; dataout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[2]~223 ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[2]~223 ; pexpout          ;
; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[3]~226 ; |serialport|baud_div:inst5|lpm_counter:delay_counter_rtl_0|dffs[3]~226 ; pexpout          ;
; |serialport|rtl~407                                                    ; |serialport|rtl~407                                                    ; pexpout          ;
; |serialport|rtl~411                                                    ; |serialport|rtl~411                                                    ; pexpout          ;
; |serialport|serialport_tx:inst7|bit_index~247                          ; |serialport|serialport_tx:inst7|bit_index~247                          ; pexpout          ;
; |serialport|baud_div:inst5|baudrate_clock~14                           ; |serialport|baud_div:inst5|baudrate_clock~14                           ; pexpout          ;
; |serialport|baud_div:inst5|baudrate_clock~19                           ; |serialport|baud_div:inst5|baudrate_clock~19                           ; pexpout          ;
; |serialport|bitnum[2]                                                  ; |serialport|bitnum[2]                                                  ; dataout          ;
; |serialport|bitnum[1]                                                  ; |serialport|bitnum[1]                                                  ; dataout          ;
; |serialport|bitnum[0]                                                  ; |serialport|bitnum[0]                                                  ; dataout          ;
; |serialport|bcd_data[3]                                                ; |serialport|bcd_data[3]                                                ; dataout          ;
; |serialport|bcd_data[2]                                                ; |serialport|bcd_data[2]                                                ; dataout          ;
; |serialport|bcd_data[1]                                                ; |serialport|bcd_data[1]                                                ; dataout          ;
; |serialport|bcd_data[0]                                                ; |serialport|bcd_data[0]                                                ; dataout          ;
; |serialport|clock_24M                                                  ; |serialport|clock_24M                                                  ; dataout          ;
; |serialport|baudrate[3]                                                ; |serialport|baudrate[3]                                                ; dataout          ;
; |serialport|baudrate[2]                                                ; |serialport|baudrate[2]                                                ; dataout          ;
; |serialport|baudrate[1]                                                ; |serialport|baudrate[1]                                                ; dataout          ;
; |serialport|baudrate[0]                                                ; |serialport|baudrate[0]                                                ; dataout          ;
; |serialport|clock_9600X2-out                                           ; |serialport|clock_9600X2-out                                           ; padio            ;
+------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 25 19:18:20 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off serialport -c serialport
Warning: Ignored node in vector source file. Can't find corresponding node name "nextState[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "nextState[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "nextState[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "nextState[0]" in design.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      29.36 %
Info: Number of transitions in simulation is 408
Info: Quartus II Simulator was successful. 0 errors, 4 warnings
    Info: Processing ended: Sun Mar 25 19:18:21 2007
    Info: Elapsed time: 00:00:02