serialport.tan.rpt

VHDL基础的编程源代码

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM3128ATC100-10   ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock_24M       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock_24M'                                                                                                                                                                                                                                                                                                       ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------+---------------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                    ; To                                                      ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------+---------------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[0]      ; serialport_tx:inst7|idata[0]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[1]      ; serialport_tx:inst7|idata[0]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[2]      ; serialport_tx:inst7|idata[0]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[0]      ; serialport_tx:inst7|idata[1]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[1]      ; serialport_tx:inst7|idata[1]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[2]      ; serialport_tx:inst7|idata[1]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[0]      ; serialport_tx:inst7|idata[2]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[1]      ; serialport_tx:inst7|idata[2]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[2]      ; serialport_tx:inst7|idata[2]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.800 ns               ;
; N/A                                     ; 47.62 MHz ( period = 21.000 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[3]      ; serialport_tx:inst7|idata[0]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.700 ns               ;
; N/A                                     ; 47.62 MHz ( period = 21.000 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[3]      ; serialport_tx:inst7|idata[1]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.700 ns               ;
; N/A                                     ; 47.62 MHz ( period = 21.000 ns )                    ; counter_out:inst|lpm_counter:counter_rtl_0|dffs[3]      ; serialport_tx:inst7|idata[2]                            ; clock_24M  ; clock_24M ; None                        ; None                      ; 12.700 ns               ;
; N/A                                     ; 49.75 MHz ( period = 20.100 ns )                    ; serialport_tx:inst7|currentState[1]                     ; serialport_tx:inst7|tx                                  ; clock_24M  ; clock_24M ; None                        ; None                      ; 15.600 ns               ;