iic.map.eqn

VHDL基础的编程源代码

--D1_sda_out is iic_controller:inst2|sda_out
D1_sda_out_p1_out = D1L47 & !D1L46 & D1L44 & D1L45;
D1_sda_out_or_out = D1_sda_out_p1_out;
D1_sda_out_reg_input = !(D1_sda_out_or_out);
D1_sda_out = DFFE(D1_sda_out_reg_input, !E1_carrier, , reset, );


--D1_send_data[0] is iic_controller:inst2|send_data[0]
D1_send_data[0]_p0_out = GLOBAL(reset) & D1_scl & !D1_currentState[3] & D1_currentState[2] & !D1_currentState[0] & D1_send_data[0] & !D1_currentState[1] & D1_data_write & !D1_data_out[0];
D1_send_data[0]_p1_out = !D1_acked & GLOBAL(reset) & D1_scl & !D1_currentState[3] & !D1_currentState[2] & D1_currentState[0] & D1_send_data[0];
D1_send_data[0]_p2_out = GLOBAL(reset) & D1_scl & !D1_currentState[3] & !D1_currentState[2] & D1_currentState[0] & D1_send_data[0] & D1_currentState[1];
D1_send_data[0]_p4_out = GLOBAL(reset) & D1_scl & !D1_currentState[3] & D1_currentState[2] & !D1_currentState[0] & D1_send_data[0] & !D1_currentState[1] & !B1_data_out[0] & !B1_data_write;
D1_send_data[0]_or_out = D1L54 # D1_send_data[0]_p0_out # D1_send_data[0]_p1_out # D1_send_data[0]_p2_out # D1_send_data[0]_p4_out;
D1_send_data[0]_reg_input = D1_send_data[0]_or_out;
D1_send_data[0] = TFFE(D1_send_data[0]_reg_input, !E1_carrier, , , );


--D1_data_out[0] is iic_controller:inst2|data_out[0]
D1_data_out[0]_p1_out = D1_send_data[0] & GLOBAL(reset) & D1_currentState[2] & !D1_currentState[1] & !D1_currentState[3] & D1_currentState[0] & D1_bit_index[3] & !D1_bit_index[1] & !D1_bit_index[2] & !D1_bit_index[0] & D1_scl & D1_acked & !D1_data_out[0];
D1_data_out[0]_p2_out = !D1_send_data[0] & GLOBAL(reset) & D1_currentState[2] & !D1_currentState[1] & !D1_currentState[3] & D1_currentState[0] & D1_bit_index[3] & !D1_bit_index[1] & !D1_bit_index[2] & !D1_bit_index[0] & D1_scl & D1_acked & D1_data_out[0];
D1_data_out[0]_or_out = D1_data_out[0]_p1_out # D1_data_out[0]_p2_out;
D1_data_out[0]_reg_input = D1_data_out[0]_or_out;
D1_data_out[0] = TFFE(D1_data_out[0]_reg_input, !E1_carrier, , , );


--B1_disp[0] is iic_app:inst|disp[0]
B1_disp[0]_p0_out = !write_read & !wr_data[0] & !B1_currentState[0];
B1_disp[0]_p1_out = !wr_data[0] & !D1_data_out[0] & D1_data_write & !B1_data_buffer[0];
B1_disp[0]_p2_out = !wr_data[0] & !B1_data_out[0] & !B1_data_write & !B1_data_buffer[0];
B1_disp[0]_p3_out = write_read & B1_currentState[1] & !D1_data_out[0] & D1_data_write;
B1_disp[0]_p4_out = write_read & B1_currentState[1] & !B1_data_out[0] & !B1_data_write;
B1_disp[0]_or_out = B1L24 # B1_disp[0]_p0_out # B1_disp[0]_p1_out # B1_disp[0]_p2_out # B1_disp[0]_p3_out # B1_disp[0]_p4_out;
B1_disp[0]_reg_input = !(B1_disp[0]_or_out);
B1_disp[0] = DFFE(B1_disp[0]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--C1L1 is seg7_leddrv:inst1|Mux~1241
C1L1_p1_out = !B1_disp[3] & !B1_disp[1] & B1_disp[2];
C1L1_p2_out = !B1_disp[3] & B1_disp[0];
C1L1_p3_out = !B1_disp[1] & !B1_disp[2] & B1_disp[0];
C1L1_or_out = C1L1_p1_out # C1L1_p2_out # C1L1_p3_out # !GLOBAL(reset);
C1L1 = C1L1_or_out;


--C1L2 is seg7_leddrv:inst1|Mux~1247
C1L2_p1_out = B1_disp[0] & B1_disp[2] & B1_disp[3] & !B1_disp[1];
C1L2_p2_out = B1_disp[0] & !B1_disp[3] & B1_disp[1];
C1L2_p3_out = !B1_disp[2] & !B1_disp[3] & B1_disp[1];
C1L2_p4_out = B1_disp[0] & !B1_disp[2] & !B1_disp[3];
C1L2_or_out = !GLOBAL(reset) # C1L2_p1_out # C1L2_p2_out # C1L2_p3_out # C1L2_p4_out;
C1L2 = C1L2_or_out;


--C1L3 is seg7_leddrv:inst1|Mux~1252
C1L3_p1_out = B1_disp[2] & B1_disp[3] & B1_disp[1];
C1L3_p2_out = B1_disp[2] & B1_disp[3] & !B1_disp[0];
C1L3_p3_out = !B1_disp[2] & !B1_disp[3] & B1_disp[1] & !B1_disp[0];
C1L3_or_out = C1L3_p1_out # C1L3_p2_out # C1L3_p3_out # !GLOBAL(reset);
C1L3 = C1L3_or_out;


--C1L4 is seg7_leddrv:inst1|Mux~1258
C1L4_p1_out = B1_disp[2] & !B1_disp[0] & B1_disp[3];
C1L4_p2_out = B1_disp[2] & !B1_disp[0] & B1_disp[1];
C1L4_p3_out = B1_disp[2] & B1_disp[0] & !B1_disp[3] & !B1_disp[1];
C1L4_p4_out = B1_disp[0] & B1_disp[3] & B1_disp[1];
C1L4_or_out = !GLOBAL(reset) # C1L4_p1_out # C1L4_p2_out # C1L4_p3_out # C1L4_p4_out;
C1L4 = C1L4_or_out;


--C1L5 is seg7_leddrv:inst1|Mux~1263
C1L5_p1_out = B1_disp[0] & B1_disp[2] & B1_disp[1] & !B1_disp[3];
C1L5_p2_out = !B1_disp[0] & B1_disp[2] & !B1_disp[1] & B1_disp[3];
C1L5_p3_out = !B1_disp[2] & !B1_disp[1] & !B1_disp[3];
C1L5_or_out = C1L5_p1_out # C1L5_p2_out # C1L5_p3_out # !GLOBAL(reset);
C1L5 = C1L5_or_out;


--C1L6 is seg7_leddrv:inst1|Mux~1269
C1L6_p1_out = !B1_disp[0] & !B1_disp[3] & !B1_disp[1] & B1_disp[2];
C1L6_p2_out = B1_disp[0] & !B1_disp[3] & !B1_disp[1] & !B1_disp[2];
C1L6_p3_out = B1_disp[0] & B1_disp[3] & !B1_disp[1] & B1_disp[2];
C1L6_p4_out = B1_disp[0] & B1_disp[3] & B1_disp[1] & !B1_disp[2];
C1L6_or_out = !GLOBAL(reset) # C1L6_p1_out # C1L6_p2_out # C1L6_p3_out # C1L6_p4_out;
C1L6 = C1L6_or_out;


--C1L7 is seg7_leddrv:inst1|Mux~1275
C1L7_p1_out = !B1_disp[0] & !B1_disp[2] & B1_disp[3] & B1_disp[1];
C1L7_p2_out = B1_disp[0] & B1_disp[2] & B1_disp[1];
C1L7_p3_out = !B1_disp[0] & B1_disp[2] & !B1_disp[3] & !B1_disp[1];
C1L7_p4_out = B1_disp[0] & !B1_disp[2] & !B1_disp[3] & !B1_disp[1];
C1L7_or_out = !GLOBAL(reset) # C1L7_p1_out # C1L7_p2_out # C1L7_p3_out # C1L7_p4_out;
C1L7 = C1L7_or_out;


--D1L5 is iic_controller:inst2|bit_index[0]~947
D1L5_p1_out = D1_currentState[0] & D1_scl & !D1_currentState[1] & D1_currentState[2] & GLOBAL(reset) & !D1_currentState[3] & !D1_bit_index[3] & D1_acked;
D1L5 = D1L5_p1_out;


--D1L7 is iic_controller:inst2|bit_index[1]~949
D1L7_p1_out = D1_bit_index[0] & D1_acked & D1_scl & !D1_currentState[1] & GLOBAL(reset) & !D1_currentState[3] & D1_currentState[2] & D1_currentState[0] & !D1_bit_index[3];
D1L7 = D1L7_p1_out;


--D1L41 is iic_controller:inst2|nextState[3]~1180
D1L41_p1_out = D1_scl & GLOBAL(reset) & !D1_currentState[3] & D1_currentState[2] & !D1_currentState[1] & !D1_currentState[0] & !D1_nextState[3];
D1L41_p2_out = D1_scl & GLOBAL(reset) & !D1_currentState[3] & !D1_currentState[2] & D1_currentState[1] & D1_currentState[0] & D1_nextState[3] & B1_wr;
D1L41 = D1L41_p1_out # D1L41_p2_out;


--D1L9 is iic_controller:inst2|bit_index[2]~951
D1L9_p1_out = D1_bit_index[1] & D1_scl & D1_bit_index[0] & D1_acked & D1_currentState[2] & D1_currentState[0] & !D1_currentState[3] & GLOBAL(reset) & !D1_currentState[1] & !D1_bit_index[3];
D1L9 = D1L9_p1_out;


--D1L11 is iic_controller:inst2|bit_index[3]~953
D1L11_p0_out = D1_bit_index[1] & D1_currentState[2] & D1_currentState[0] & GLOBAL(reset) & D1_currentState[1] & D1_currentState[3] & D1_bit_index[3];
D1L11_p1_out = D1_acked & D1_bit_index[1] & D1_bit_index[2] & D1_bit_index[0] & D1_currentState[2] & D1_currentState[0] & GLOBAL(reset) & !D1_currentState[1] & D1_scl & !D1_currentState[3] & !D1_bit_index[3];
D1L11_p2_out = D1_bit_index[1] & D1_bit_index[2] & D1_bit_index[0] & D1_currentState[2] & D1_currentState[0] & GLOBAL(reset) & D1_currentState[1] & !D1_scl & D1_currentState[3];
D1L11_p3_out = D1_acked & !D1_bit_index[1] & !D1_bit_index[2] & !D1_bit_index[0] & D1_currentState[2] & GLOBAL(reset) & !D1_currentState[1] & D1_scl & !D1_currentState[3] & D1_bit_index[3];
D1L11_p4_out = !D1_currentState[2] & D1_currentState[0] & GLOBAL(reset) & D1_scl & !D1_currentState[3] & D1_bit_index[3];
D1L11 = D1L11_p0_out # D1L11_p1_out # D1L11_p2_out # D1L11_p3_out # D1L11_p4_out;


--D1L17 is iic_controller:inst2|currentState~3901
D1L17_p1_out = D1_acked & !D1_currentState[1] & D1_scl & D1_currentState[0] & D1_bit_index[3] & !D1_bit_index[1] & !D1_bit_index[2] & !D1_bit_index[0];
D1L17_p2_out = !D1_currentState[1] & D1_scl & !D1_currentState[0] & D1_currentState[2];
D1L17 = D1L17_p1_out # D1L17_p2_out;


--D1L18 is iic_controller:inst2|currentState~3904
D1L18_p0_out = D1_acked & D1_scl & !D1_currentState[0] & D1_currentState[3];
D1L18_p1_out = D1_acked & !D1_currentState[2] & D1_scl & D1_currentState[0];
D1L18_p2_out = !D1_currentState[2] & D1_scl & D1_currentState[0] & !B1_rd;
D1L18_p3_out = !D1_currentState[2] & D1_scl & D1_currentState[0] & !D1_send_devaddr_again_flag;
D1L18_p4_out = !D1_currentState[2] & D1_scl & D1_currentState[0] & D1_currentState[1];
D1L18 = D1L17 # D1L18_p0_out # D1L18_p1_out # D1L18_p2_out # D1L18_p3_out # D1L18_p4_out;


--D1L2 is iic_controller:inst2|acked~651
D1L2_p1_out = B1_wr & D1_currentState[1] & GLOBAL(reset) & D1_currentState[2] & D1_scl & !D1_currentState[0] & D1_currentState[3] & !D1_acked;
D1L2 = D1L2_p1_out;


--D1L37 is iic_controller:inst2|nextState[1]~1183
D1L37_p1_out = !D1_currentState[1] & D1_scl & GLOBAL(reset) & !D1_currentState[3] & D1_currentState[2] & !D1_currentState[0] & !D1_nextState[1];
D1L37_p2_out = !D1_currentState[1] & D1_scl & GLOBAL(reset) & !D1_currentState[3] & !D1_currentState[2] & D1_currentState[0] & !D1_nextState[1] & !B1_rd;
D1L37 = D1L37_p1_out # D1L37_p2_out;


--D1L35 is iic_controller:inst2|nextState[0]~1186
D1L35_p1_out = D1_acked & D1_scl & GLOBAL(reset) & !D1_currentState[3] & !D1_currentState[2] & !D1_currentState[1] & D1_currentState[0] & !D1_nextState[0];
D1L35_p2_out = D1_scl & GLOBAL(reset) & !D1_currentState[3] & !D1_currentState[2] & !D1_currentState[1] & D1_currentState[0] & !D1_nextState[0] & !B1_rd;
D1L35 = D1L35_p1_out # D1L35_p2_out;


--D1L39 is iic_controller:inst2|nextState[2]~1189
D1L39_p1_out = D1_acked & D1_send_devaddr_again_flag & B1_rd & !D1_currentState[3] & !D1_currentState[1] & !D1_currentState[2] & D1_currentState[0] & D1_scl & GLOBAL(reset) & !D1_nextState[2];
D1L39_p2_out = !D1_currentState[3] & D1_currentState[1] & !D1_currentState[2] & D1_currentState[0] & D1_scl & GLOBAL(reset) & !D1_nextState[2] & B1_wr;
D1L39 = D1L39_p1_out # D1L39_p2_out;


--D1L19 is iic_controller:inst2|currentState~3910
D1L19_p1_out = !B1_rd & !B1_wr & !D1_currentState[0] & !D1_currentState[2];
D1L19_p2_out = !D1_currentState[0] & D1_currentState[2] & !D1_scl;
D1L19_p3_out = D1_currentState[0] & D1_currentState[2] & D1_scl & D1_acked & D1_bit_index[3] & !D1_bit_index[1] & !D1_bit_index[2] & !D1_currentState[1] & !D1_bit_index[0];
D1L19_p4_out = !D1_currentState[0] & D1_currentState[1];
D1L19 = D1L19_p1_out # D1L19_p2_out # D1L19_p3_out # D1L19_p4_out;


--B1L20 is iic_app:inst|disp~2013
B1L20_p0_out = B1_currentState[0] & !B1_currentState[1] & !B1_data_buffer[2];
B1L20_p1_out = B1_rd & D1_stop & D1_data_write & !D1_data_out[2] & B1_currentState[0] & B1_currentState[1];
B1L20_p2_out = D1_data_write & !D1_data_out[2] & B1_currentState[1] & write_read;
B1L20_p3_out = B1_rd & D1_stop & B1_currentState[0] & B1_currentState[1] & !B1_data_write & !B1_data_out[2];
B1L20_p4_out = B1_currentState[1] & write_read & !B1_data_write & !B1_data_out[2];
B1L20 = B1L20_p0_out # B1L20_p1_out # B1L20_p2_out # B1L20_p3_out # B1L20_p4_out;