iic.map.qmsg

VHDL基础的编程源代码

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[4\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[4\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[4\] data_in GND " "Warning: Reduced register \"iic_app:inst\|dev_addr\[4\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[5\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[5\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "iic_app:inst\|dev_addr\[5\] High " "Info: Power-up level of register \"iic_app:inst\|dev_addr\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[5\] data_in VCC " "Warning: Reduced register \"iic_app:inst\|dev_addr\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[6\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[6\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[6\] data_in GND " "Warning: Reduced register \"iic_app:inst\|dev_addr\[6\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[7\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[7\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "iic_app:inst\|dev_addr\[7\] High " "Info: Power-up level of register \"iic_app:inst\|dev_addr\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[7\] data_in VCC " "Warning: Reduced register \"iic_app:inst\|dev_addr\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|data_out\[4\] data_in GND " "Warning: Reduced register \"iic_app:inst\|data_out\[4\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|data_out\[5\] data_in GND " "Warning: Reduced register \"iic_app:inst\|data_out\[5\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|data_out\[6\] data_in GND " "Warning: Reduced register \"iic_app:inst\|data_out\[6\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|data_out\[7\] data_in GND " "Warning: Reduced register \"iic_app:inst\|data_out\[7\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "6 " "Info: Ignored 6 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "6 " "Info: Ignored 6 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_app:inst\|data_out_tmp~12 " "Warning: Converting TRI node \"iic_app:inst\|data_out_tmp~12\" that feeds logic to an OR gate" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 76 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_app:inst\|data_out_tmp~16 " "Warning: Converting TRI node \"iic_app:inst\|data_out_tmp~16\" that feeds logic to an OR gate" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 76 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_app:inst\|data_out_tmp~20 " "Warning: Converting TRI node \"iic_app:inst\|data_out_tmp~20\" that feeds logic to an OR gate" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 76 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_app:inst\|data_out_tmp~24 " "Warning: Converting TRI node \"iic_app:inst\|data_out_tmp~24\" that feeds logic to an OR gate" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 76 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_controller:inst2\|data_out_tmp~12 " "Warning: Converting TRI node \"iic_controller:inst2\|data_out_tmp~12\" that feeds logic to an OR gate" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 69 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_controller:inst2\|data_out_tmp~16 " "Warning: Converting TRI node \"iic_controller:inst2\|data_out_tmp~16\" that feeds logic to an OR gate" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 69 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_controller:inst2\|data_out_tmp~20 " "Warning: Converting TRI node \"iic_controller:inst2\|data_out_tmp~20\" that feeds logic to an OR gate" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 69 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iic_controller:inst2\|data_out_tmp~24 " "Warning: Converting TRI node \"iic_controller:inst2\|data_out_tmp~24\" that feeds logic to an OR gate" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 69 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 51 -1 0 } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 72 -1 0 } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 71 -1 0 } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 74 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock_24M " "Info: Promoted clock signal driven by pin \"clock_24M\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "130 " "Info: Implemented 130 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "107 " "Info: Implemented 107 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 39 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 39 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 27 11:40:37 2007 " "Info: Processing ended: Tue Mar 27 11:40:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}