iic.map.qmsg

VHDL基础的编程源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 27 11:40:24 2007 " "Info: Processing started: Tue Mar 27 11:40:24 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off iic -c iic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off iic -c iic" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_leddrv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_leddrv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_leddrv-seg7_leddrv_architecture " "Info: Found design unit 1: seg7_leddrv-seg7_leddrv_architecture" {  } { { "seg7_leddrv.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/seg7_leddrv.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_leddrv " "Info: Found entity 1: seg7_leddrv" {  } { { "seg7_leddrv.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/seg7_leddrv.vhd" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "iic.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file iic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 iic " "Info: Found entity 1: iic" {  } { { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_architecture " "Info: Found design unit 1: counter-counter_architecture" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "iic_controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file iic_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 iic_controller-iic_controller_architecture " "Info: Found design unit 1: iic_controller-iic_controller_architecture" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 iic_controller " "Info: Found entity 1: iic_controller" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "iic_app.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file iic_app.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 iic_app-iic_app_architecture " "Info: Found design unit 1: iic_app-iic_app_architecture" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 73 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 iic_app " "Info: Found entity 1: iic_app" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "iic " "Info: Elaborating entity \"iic\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rd iic_app inst " "Warning: Port \"rd\" of type iic_app and instance \"inst\" is missing source signal" {  } { { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -2008 280 472 -1848 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "wr iic_app inst " "Warning: Port \"wr\" of type iic_app and instance \"inst\" is missing source signal" {  } { { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -2008 280 472 -1848 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst3 " "Warning: Port \"carrier\" of type counter and instance \"inst3\" is missing source signal" {  } { { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1992 24 168 -1896 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst3 " "Warning: Port \"counter\" of type counter and instance \"inst3\" is missing source signal" {  } { { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1992 24 168 -1896 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "scl iic_controller inst2 " "Warning: Port \"scl\" of type iic_controller and instance \"inst2\" is missing source signal" {  } { { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -2008 536 712 -1848 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "iic_controller iic_controller:inst2 " "Info: Elaborating entity \"iic_controller\" for hierarchy \"iic_controller:inst2\"" {  } { { "iic.bdf" "inst2" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -2008 536 712 -1848 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "iic_app iic_app:inst " "Info: Elaborating entity \"iic_app\" for hierarchy \"iic_app:inst\"" {  } { { "iic.bdf" "inst" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -2008 280 472 -1848 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data_buffer\[7\] X iic_app.vhd(84) " "Warning (10030): Tied undriven net \"data_buffer\[7\]\" at iic_app.vhd(84) to X" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 84 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data_buffer\[6\] X iic_app.vhd(84) " "Warning (10030): Tied undriven net \"data_buffer\[6\]\" at iic_app.vhd(84) to X" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 84 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data_buffer\[5\] X iic_app.vhd(84) " "Warning (10030): Tied undriven net \"data_buffer\[5\]\" at iic_app.vhd(84) to X" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 84 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data_buffer\[4\] X iic_app.vhd(84) " "Warning (10030): Tied undriven net \"data_buffer\[4\]\" at iic_app.vhd(84) to X" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 84 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst3 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst3\"" {  } { { "iic.bdf" "inst3" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1992 24 168 -1896 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset counter.vhd(63) " "Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7_leddrv seg7_leddrv:inst1 " "Info: Elaborating entity \"seg7_leddrv\" for hierarchy \"seg7_leddrv:inst1\"" {  } { { "iic.bdf" "inst1" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1776 528 720 -1680 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "seg7_leddrv.vhd(69) " "Info (10425): VHDL Case Statement information at seg7_leddrv.vhd(69): OTHERS choice is never selected" {  } { { "seg7_leddrv.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/seg7_leddrv.vhd" 69 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|currentState\[2\] data_in GND " "Warning: Reduced register \"iic_app:inst\|currentState\[2\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[0\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[0\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[0\] data_in GND " "Warning: Reduced register \"iic_app:inst\|dev_addr\[0\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[1\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[1\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[1\] data_in GND " "Warning: Reduced register \"iic_app:inst\|dev_addr\[1\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[2\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[2\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[2\] data_in GND " "Warning: Reduced register \"iic_app:inst\|dev_addr\[2\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|mem_addr\[3\] data_in GND " "Warning: Reduced register \"iic_app:inst\|mem_addr\[3\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "iic_app:inst\|dev_addr\[3\] data_in GND " "Warning: Reduced register \"iic_app:inst\|dev_addr\[3\]\" with stuck data_in port to stuck value GND" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}