iic.tan.qmsg

VHDL基础的编程源代码

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "iic_app:inst\|data_out\[1\] iic_controller:inst2\|send_data\[1\] clock_24M 900 ps " "Info: Found hold time violation between source  pin or register \"iic_app:inst\|data_out\[1\]\" and destination pin or register \"iic_controller:inst2\|send_data\[1\]\" for clock \"clock_24M\" (Hold time is 900 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.900 ns + Largest " "Info: + Largest clock skew is 6.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.300 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { clock_24M } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst3\|carrier 2 REG LC81 36 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC81; Fanout = 36; REG Node = 'counter:inst3\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "2.500 ns" { clock_24M counter:inst3|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.200 ns) 10.300 ns iic_controller:inst2\|send_data\[1\] 3 REG LC34 13 " "Info: 3: + IC(3.100 ns) + CELL(2.200 ns) = 10.300 ns; Loc. = LC34; Fanout = 13; REG Node = 'iic_controller:inst2\|send_data\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "5.300 ns" { counter:inst3|carrier iic_controller:inst2|send_data[1] } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 69.90 % ) " "Info: Total cell delay = 7.200 ns ( 69.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 30.10 % ) " "Info: Total interconnect delay = 3.100 ns ( 30.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|send_data[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|send_data[1] } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { clock_24M } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns iic_app:inst\|data_out\[1\] 2 REG LC47 6 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC47; Fanout = 6; REG Node = 'iic_app:inst\|data_out\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "0.900 ns" { clock_24M iic_app:inst|data_out[1] } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|data_out[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|data_out[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|send_data[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|send_data[1] } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|data_out[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|data_out[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns - Shortest register register " "Info: - Shortest register to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iic_app:inst\|data_out\[1\] 1 REG LC47 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC47; Fanout = 6; REG Node = 'iic_app:inst\|data_out\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { iic_app:inst|data_out[1] } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 5.700 ns iic_controller:inst2\|send_data\[1\] 2 REG LC34 13 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 5.700 ns; Loc. = LC34; Fanout = 13; REG Node = 'iic_controller:inst2\|send_data\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "5.700 ns" { iic_app:inst|data_out[1] iic_controller:inst2|send_data[1] } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 54.39 % ) " "Info: Total cell delay = 3.100 ns ( 54.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 45.61 % ) " "Info: Total interconnect delay = 2.600 ns ( 45.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "5.700 ns" { iic_app:inst|data_out[1] iic_controller:inst2|send_data[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.700 ns" { iic_app:inst|data_out[1] iic_controller:inst2|send_data[1] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 104 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 104 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|send_data[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|send_data[1] } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|data_out[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|data_out[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "5.700 ns" { iic_app:inst|data_out[1] iic_controller:inst2|send_data[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.700 ns" { iic_app:inst|data_out[1] iic_controller:inst2|send_data[1] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "iic_app:inst\|disp\[2\] write_read clock_24M 7.800 ns register " "Info: tsu for register \"iic_app:inst\|disp\[2\]\" (data pin = \"write_read\", clock pin = \"clock_24M\") is 7.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.300 ns + Longest pin register " "Info: + Longest pin to register delay is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns write_read 1 PIN PIN_97 37 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_97; Fanout = 37; PIN Node = 'write_read'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { write_read } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1736 -152 16 -1720 "write_read" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.300 ns) 5.600 ns iic_app:inst\|disp~2013 2 COMB LC82 1 " "Info: 2: + IC(2.900 ns) + CELL(1.300 ns) = 5.600 ns; Loc. = LC82; Fanout = 1; COMB Node = 'iic_app:inst\|disp~2013'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "4.200 ns" { write_read iic_app:inst|disp~2013 } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 8.300 ns iic_app:inst\|disp\[2\] 3 REG LC83 22 " "Info: 3: + IC(0.000 ns) + CELL(2.700 ns) = 8.300 ns; Loc. = LC83; Fanout = 22; REG Node = 'iic_app:inst\|disp\[2\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "2.700 ns" { iic_app:inst|disp~2013 iic_app:inst|disp[2] } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns ( 65.06 % ) " "Info: Total cell delay = 5.400 ns ( 65.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 34.94 % ) " "Info: Total interconnect delay = 2.900 ns ( 34.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "8.300 ns" { write_read iic_app:inst|disp~2013 iic_app:inst|disp[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.300 ns" { write_read write_read~out iic_app:inst|disp~2013 iic_app:inst|disp[2] } { 0.000ns 0.000ns 2.900ns 0.000ns } { 0.000ns 1.400ns 1.300ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { clock_24M } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns iic_app:inst\|disp\[2\] 2 REG LC83 22 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC83; Fanout = 22; REG Node = 'iic_app:inst\|disp\[2\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "0.900 ns" { clock_24M iic_app:inst|disp[2] } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|disp[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|disp[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "8.300 ns" { write_read iic_app:inst|disp~2013 iic_app:inst|disp[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.300 ns" { write_read write_read~out iic_app:inst|disp~2013 iic_app:inst|disp[2] } { 0.000ns 0.000ns 2.900ns 0.000ns } { 0.000ns 1.400ns 1.300ns 2.700ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|disp[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|disp[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M sda iic_controller:inst2\|sda_write 19.500 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"sda\" through register \"iic_controller:inst2\|sda_write\" is 19.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 10.300 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { clock_24M } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst3\|carrier 2 REG LC81 36 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC81; Fanout = 36; REG Node = 'counter:inst3\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "2.500 ns" { clock_24M counter:inst3|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.200 ns) 10.300 ns iic_controller:inst2\|sda_write 3 REG LC128 11 " "Info: 3: + IC(3.100 ns) + CELL(2.200 ns) = 10.300 ns; Loc. = LC128; Fanout = 11; REG Node = 'iic_controller:inst2\|sda_write'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "5.300 ns" { counter:inst3|carrier iic_controller:inst2|sda_write } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 69.90 % ) " "Info: Total cell delay = 7.200 ns ( 69.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 30.10 % ) " "Info: Total interconnect delay = 3.100 ns ( 30.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|sda_write } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|sda_write } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register pin " "Info: + Longest register to pin delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iic_controller:inst2\|sda_write 1 REG LC128 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC128; Fanout = 11; REG Node = 'iic_controller:inst2\|sda_write'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { iic_controller:inst2|sda_write } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(5.000 ns) 7.600 ns sda 2 PIN PIN_99 0 " "Info: 2: + IC(2.600 ns) + CELL(5.000 ns) = 7.600 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'sda'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "7.600 ns" { iic_controller:inst2|sda_write sda } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 728 904 -1952 "sda" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 65.79 % ) " "Info: Total cell delay = 5.000 ns ( 65.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 34.21 % ) " "Info: Total interconnect delay = 2.600 ns ( 34.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "7.600 ns" { iic_controller:inst2|sda_write sda } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { iic_controller:inst2|sda_write sda } { 0.000ns 2.600ns } { 0.000ns 5.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|sda_write } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|sda_write } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "7.600 ns" { iic_controller:inst2|sda_write sda } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { iic_controller:inst2|sda_write sda } { 0.000ns 2.600ns } { 0.000ns 5.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset seg7led_bits\[3\] 10.600 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"seg7led_bits\[3\]\" is 10.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 183 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 183; PIN Node = 'reset'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { reset } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1952 -160 8 -1936 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.400 ns) 9.000 ns seg7_leddrv:inst1\|Mux~1275 2 COMB LC105 1 " "Info: 2: + IC(2.100 ns) + CELL(4.400 ns) = 9.000 ns; Loc. = LC105; Fanout = 1; COMB Node = 'seg7_leddrv:inst1\|Mux~1275'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "6.500 ns" { reset seg7_leddrv:inst1|Mux~1275 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.600 ns seg7led_bits\[3\] 3 PIN PIN_69 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.600 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'seg7led_bits\[3\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "1.600 ns" { seg7_leddrv:inst1|Mux~1275 seg7led_bits[3] } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1752 720 902 -1736 "seg7led_bits\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 80.19 % ) " "Info: Total cell delay = 8.500 ns ( 80.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns ( 19.81 % ) " "Info: Total interconnect delay = 2.100 ns ( 19.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.600 ns" { reset seg7_leddrv:inst1|Mux~1275 seg7led_bits[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.600 ns" { reset reset~out seg7_leddrv:inst1|Mux~1275 seg7led_bits[3] } { 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 2.500ns 4.400ns 1.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "iic_controller:inst2\|send_data\[7\] sda clock_24M 4.200 ns register " "Info: th for register \"iic_controller:inst2\|send_data\[7\]\" (data pin = \"sda\", clock pin = \"clock_24M\") is 4.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.300 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { clock_24M } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst3\|carrier 2 REG LC81 36 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC81; Fanout = 36; REG Node = 'counter:inst3\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "2.500 ns" { clock_24M counter:inst3|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.200 ns) 10.300 ns iic_controller:inst2\|send_data\[7\] 3 REG LC3 12 " "Info: 3: + IC(3.100 ns) + CELL(2.200 ns) = 10.300 ns; Loc. = LC3; Fanout = 12; REG Node = 'iic_controller:inst2\|send_data\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "5.300 ns" { counter:inst3|carrier iic_controller:inst2|send_data[7] } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 69.90 % ) " "Info: Total cell delay = 7.200 ns ( 69.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 30.10 % ) " "Info: Total interconnect delay = 3.100 ns ( 30.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|send_data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|send_data[7] } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 104 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_99 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_99; Fanout = 1; PIN Node = 'sda'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { sda } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 728 904 -1952 "sda" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns sda~0 2 COMB IO6 16 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = IO6; Fanout = 16; COMB Node = 'sda~0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "1.400 ns" { sda sda~0 } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 728 904 -1952 "sda" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.100 ns) 7.400 ns iic_controller:inst2\|send_data\[7\] 3 REG LC3 12 " "Info: 3: + IC(2.900 ns) + CELL(3.100 ns) = 7.400 ns; Loc. = LC3; Fanout = 12; REG Node = 'iic_controller:inst2\|send_data\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "6.000 ns" { sda~0 iic_controller:inst2|send_data[7] } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 60.81 % ) " "Info: Total cell delay = 4.500 ns ( 60.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 39.19 % ) " "Info: Total interconnect delay = 2.900 ns ( 39.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "7.400 ns" { sda sda~0 iic_controller:inst2|send_data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.400 ns" { sda sda~0 iic_controller:inst2|send_data[7] } { 0.000ns 0.000ns 2.900ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|send_data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|send_data[7] } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "7.400 ns" { sda sda~0 iic_controller:inst2|send_data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.400 ns" { sda sda~0 iic_controller:inst2|send_data[7] } { 0.000ns 0.000ns 2.900ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}