iic.tan.qmsg

VHDL基础的编程源代码

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock_24M " "Info: Assuming node \"clock_24M\" is an undefined clock" {  } { { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock_24M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter:inst3\|carrier " "Info: Detected ripple clock \"counter:inst3\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst3\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register iic_controller:inst2\|stop register iic_app:inst\|disp\[0\] 26.18 MHz 38.2 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 26.18 MHz between source register \"iic_controller:inst2\|stop\" and destination register \"iic_app:inst\|disp\[0\]\" (period= 38.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Longest register register " "Info: + Longest register to register delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iic_controller:inst2\|stop 1 REG LC32 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 18; REG Node = 'iic_controller:inst2\|stop'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { iic_controller:inst2|stop } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.300 ns) 4.100 ns iic_app:inst\|disp~2031 2 COMB LC22 1 " "Info: 2: + IC(2.800 ns) + CELL(1.300 ns) = 4.100 ns; Loc. = LC22; Fanout = 1; COMB Node = 'iic_app:inst\|disp~2031'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "4.100 ns" { iic_controller:inst2|stop iic_app:inst|disp~2031 } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 5.000 ns iic_app:inst\|disp~2034 3 COMB LC23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 5.000 ns; Loc. = LC23; Fanout = 1; COMB Node = 'iic_app:inst\|disp~2034'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "0.900 ns" { iic_app:inst|disp~2031 iic_app:inst|disp~2034 } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 7.700 ns iic_app:inst\|disp\[0\] 4 REG LC24 21 " "Info: 4: + IC(0.000 ns) + CELL(2.700 ns) = 7.700 ns; Loc. = LC24; Fanout = 21; REG Node = 'iic_app:inst\|disp\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "2.700 ns" { iic_app:inst|disp~2034 iic_app:inst|disp[0] } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns ( 63.64 % ) " "Info: Total cell delay = 4.900 ns ( 63.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 36.36 % ) " "Info: Total interconnect delay = 2.800 ns ( 36.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "7.700 ns" { iic_controller:inst2|stop iic_app:inst|disp~2031 iic_app:inst|disp~2034 iic_app:inst|disp[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.700 ns" { iic_controller:inst2|stop iic_app:inst|disp~2031 iic_app:inst|disp~2034 iic_app:inst|disp[0] } { 0.000ns 2.800ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.900 ns - Smallest " "Info: - Smallest clock skew is -6.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { clock_24M } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns iic_app:inst\|disp\[0\] 2 REG LC24 21 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC24; Fanout = 21; REG Node = 'iic_app:inst\|disp\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "0.900 ns" { clock_24M iic_app:inst|disp[0] } "NODE_NAME" } "" } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|disp[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|disp[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 10.300 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "" { clock_24M } "NODE_NAME" } "" } } { "iic.bdf" "" { Schematic "H:/03-源码文件/VHDL/15-IIC读写/iic.bdf" { { -1968 -160 8 -1952 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst3\|carrier 2 REG LC81 36 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC81; Fanout = 36; REG Node = 'counter:inst3\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "2.500 ns" { clock_24M counter:inst3|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.200 ns) 10.300 ns iic_controller:inst2\|stop 3 REG LC32 18 " "Info: 3: + IC(3.100 ns) + CELL(2.200 ns) = 10.300 ns; Loc. = LC32; Fanout = 18; REG Node = 'iic_controller:inst2\|stop'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "5.300 ns" { counter:inst3|carrier iic_controller:inst2|stop } "NODE_NAME" } "" } } { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 69.90 % ) " "Info: Total cell delay = 7.200 ns ( 69.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 30.10 % ) " "Info: Total interconnect delay = 3.100 ns ( 30.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|stop } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|stop } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|disp[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|disp[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|stop } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|stop } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "iic_controller.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_controller.vhd" 49 -1 0 } } { "iic_app.vhd" "" { Text "H:/03-源码文件/VHDL/15-IIC读写/iic_app.vhd" 87 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "7.700 ns" { iic_controller:inst2|stop iic_app:inst|disp~2031 iic_app:inst|disp~2034 iic_app:inst|disp[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.700 ns" { iic_controller:inst2|stop iic_app:inst|disp~2031 iic_app:inst|disp~2034 iic_app:inst|disp[0] } { 0.000ns 2.800ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "3.400 ns" { clock_24M iic_app:inst|disp[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out iic_app:inst|disp[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "iic" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/15-IIC读写/db/iic.quartus_db" { Floorplan "H:/03-源码文件/VHDL/15-IIC读写/" "" "10.300 ns" { clock_24M counter:inst3|carrier iic_controller:inst2|stop } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.300 ns" { clock_24M clock_24M~out counter:inst3|carrier iic_controller:inst2|stop } { 0.000ns 0.000ns 0.000ns 3.100ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock_24M 28 " "Warning: Circuit may not operate. Detected 28 non-operational path(s) clocked by clock \"clock_24M\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}