iic.hier_info

VHDL基础的编程源代码

|iic
scl <= iic_controller:inst2.scl
write_read => iic_app:inst.write_read
write_read => inst9.IN0
write_read => led_cs[3].DATAIN
write_read => led_cs[4].DATAIN
write_read => led_cs[5].DATAIN
write_read => seg7_leddrv:inst1.dp
clock_24M => iic_app:inst.clock
clock_24M => counter:inst3.clock
reset => iic_app:inst.reset
reset => counter:inst3.reset
reset => iic_controller:inst2.reset
reset => seg7_leddrv:inst1.reset
wr_data[0] => iic_app:inst.wr_data[0]
wr_data[1] => iic_app:inst.wr_data[1]
wr_data[2] => iic_app:inst.wr_data[2]
wr_data[3] => iic_app:inst.wr_data[3]
sda <= iic_controller:inst2.sda
led_cs[0] <= inst9.DB_MAX_OUTPUT_PORT_TYPE
led_cs[1] <= inst9.DB_MAX_OUTPUT_PORT_TYPE
led_cs[2] <= inst9.DB_MAX_OUTPUT_PORT_TYPE
led_cs[3] <= write_read.DB_MAX_OUTPUT_PORT_TYPE
led_cs[4] <= write_read.DB_MAX_OUTPUT_PORT_TYPE
led_cs[5] <= write_read.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[0] <= seg7_leddrv:inst1.seg7led_bits[0]
seg7led_bits[1] <= seg7_leddrv:inst1.seg7led_bits[1]
seg7led_bits[2] <= seg7_leddrv:inst1.seg7led_bits[2]
seg7led_bits[3] <= seg7_leddrv:inst1.seg7led_bits[3]
seg7led_bits[4] <= seg7_leddrv:inst1.seg7led_bits[4]
seg7led_bits[5] <= seg7_leddrv:inst1.seg7led_bits[5]
seg7led_bits[6] <= seg7_leddrv:inst1.seg7led_bits[6]
seg7led_bits[7] <= seg7_leddrv:inst1.seg7led_bits[7]


|iic|iic_controller:inst2
scl <= scl~reg0.DB_MAX_OUTPUT_PORT_TYPE
sda <= sda_out_tmp~0
data[0] <= data_out_tmp~7
data[1] <= data_out_tmp~6
data[2] <= data_out_tmp~5
data[3] <= data_out_tmp~4
data[4] <= data_out_tmp~3
data[5] <= data_out_tmp~2
data[6] <= data_out_tmp~1
data[7] <= data_out_tmp~0
stop <= stop~reg0.DB_MAX_OUTPUT_PORT_TYPE
rd => process1~0.IN0
rd => data_write~1.OUTPUTSELECT
rd => process1~1.IN0
rd => nextState~12.OUTPUTSELECT
rd => nextState~13.OUTPUTSELECT
rd => nextState~14.OUTPUTSELECT
rd => nextState~15.OUTPUTSELECT
rd => send_devaddr_again_flag~3.OUTPUTSELECT
wr => process1~0.IN1
wr => data_write~0.OUTPUTSELECT
wr => nextState~16.OUTPUTSELECT
wr => nextState~17.OUTPUTSELECT
wr => nextState~18.OUTPUTSELECT
wr => nextState~19.OUTPUTSELECT
wr => send_devaddr_again_flag~4.OUTPUTSELECT
wr => process1~3.IN1
dev_addr[0] => send_data~0.DATAB
dev_addr[1] => send_data~8.DATAB
dev_addr[2] => send_data~7.DATAB
dev_addr[3] => send_data~6.DATAB
dev_addr[4] => send_data~5.DATAB
dev_addr[5] => send_data~4.DATAB
dev_addr[6] => send_data~3.DATAB
dev_addr[7] => send_data~2.DATAB
addr[0] => send_data~17.DATAB
addr[1] => send_data~16.DATAB
addr[2] => send_data~15.DATAB
addr[3] => send_data~14.DATAB
addr[4] => send_data~13.DATAB
addr[5] => send_data~12.DATAB
addr[6] => send_data~11.DATAB
addr[7] => send_data~10.DATAB
clock => process0~1.IN0
clock => currentState[2].CLK
clock => currentState[1].CLK
clock => currentState[0].CLK
clock => stop~reg0.CLK
clock => sda_write.CLK
clock => sda_out.CLK
clock => send_devaddr_again_flag.CLK
clock => data_write.CLK
clock => send_data[7].CLK
clock => send_data[6].CLK
clock => send_data[5].CLK
clock => send_data[4].CLK
clock => send_data[3].CLK
clock => send_data[2].CLK
clock => send_data[1].CLK
clock => send_data[0].CLK
clock => bit_index[3].CLK
clock => bit_index[2].CLK
clock => bit_index[1].CLK
clock => bit_index[0].CLK
clock => acked.CLK
clock => nextState[3].CLK
clock => nextState[2].CLK
clock => nextState[1].CLK
clock => nextState[0].CLK
clock => data_out[7].CLK
clock => data_out[6].CLK
clock => data_out[5].CLK
clock => data_out[4].CLK
clock => data_out[3].CLK
clock => data_out[2].CLK
clock => data_out[1].CLK
clock => data_out[0].CLK
clock => currentState[3].CLK
reset => process0~0.IN0


|iic|iic_app:inst
rd <= rd~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr <= wr~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[0] <= dev_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[1] <= dev_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[2] <= dev_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[3] <= dev_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[4] <= dev_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[5] <= dev_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[6] <= dev_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dev_addr[7] <= dev_addr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[0] <= mem_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[1] <= mem_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[2] <= mem_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[3] <= mem_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[4] <= mem_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[5] <= mem_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[6] <= mem_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_addr[7] <= mem_addr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data_out_tmp~7
data[1] <= data_out_tmp~6
data[2] <= data_out_tmp~5
data[3] <= data_out_tmp~4
data[4] <= data_out_tmp~3
data[5] <= data_out_tmp~2
data[6] <= data_out_tmp~1
data[7] <= data_out_tmp~0
disp[0] <= disp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[1] <= disp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[2] <= disp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[3] <= disp[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stop => disp~8.OUTPUTSELECT
stop => disp~9.OUTPUTSELECT
stop => disp~10.OUTPUTSELECT
stop => disp~11.OUTPUTSELECT
stop => rd~0.OUTPUTSELECT
stop => wr~0.OUTPUTSELECT
write_read => currentState~7.DATAB
write_read => process0~1.IN0
wr_data[0] => disp~3.DATAB
wr_data[0] => data_buffer~3.DATAB
wr_data[1] => disp~2.DATAB
wr_data[1] => data_buffer~2.DATAB
wr_data[2] => disp~1.DATAB
wr_data[2] => data_buffer~1.DATAB
wr_data[3] => disp~0.DATAB
wr_data[3] => data_buffer~0.DATAB
clock => disp[2]~reg0.CLK
clock => disp[1]~reg0.CLK
clock => disp[0]~reg0.CLK
clock => currentState[2].CLK
clock => currentState[1].CLK
clock => currentState[0].CLK
clock => wr~reg0.CLK
clock => rd~reg0.CLK
clock => data_write.CLK
clock => data_out[7].CLK
clock => data_out[6].CLK
clock => data_out[5].CLK
clock => data_out[4].CLK
clock => data_out[3].CLK
clock => data_out[2].CLK
clock => data_out[1].CLK
clock => data_out[0].CLK
clock => data_buffer[3].CLK
clock => data_buffer[2].CLK
clock => data_buffer[1].CLK
clock => data_buffer[0].CLK
clock => dev_addr[7]~reg0.CLK
clock => dev_addr[6]~reg0.CLK
clock => dev_addr[5]~reg0.CLK
clock => dev_addr[4]~reg0.CLK
clock => dev_addr[3]~reg0.CLK
clock => dev_addr[2]~reg0.CLK
clock => dev_addr[1]~reg0.CLK
clock => dev_addr[0]~reg0.CLK
clock => mem_addr[7]~reg0.CLK
clock => mem_addr[6]~reg0.CLK
clock => mem_addr[5]~reg0.CLK
clock => mem_addr[4]~reg0.CLK
clock => mem_addr[3]~reg0.CLK
clock => mem_addr[2]~reg0.CLK
clock => mem_addr[1]~reg0.CLK
clock => mem_addr[0]~reg0.CLK
clock => disp[3]~reg0.CLK
reset => process0~0.IN0


|iic|counter:inst3
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE


|iic|seg7_leddrv:inst1
seg7led_bits[0] <= seg7led_bits~7.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[1] <= seg7led_bits~6.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[2] <= seg7led_bits~5.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[3] <= seg7led_bits~4.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[4] <= seg7led_bits~3.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[5] <= seg7led_bits~2.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[6] <= seg7led_bits~1.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[7] <= seg7led_bits~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Mux~0.IN19
data[0] => Mux~1.IN19
data[0] => Mux~2.IN19
data[0] => Mux~3.IN19
data[0] => Mux~4.IN19
data[0] => Mux~5.IN19
data[0] => Mux~6.IN19
data[1] => Mux~0.IN18
data[1] => Mux~1.IN18
data[1] => Mux~2.IN18
data[1] => Mux~3.IN18
data[1] => Mux~4.IN18
data[1] => Mux~5.IN18
data[1] => Mux~6.IN18
data[2] => Mux~0.IN17
data[2] => Mux~1.IN17
data[2] => Mux~2.IN17
data[2] => Mux~3.IN17
data[2] => Mux~4.IN17
data[2] => Mux~5.IN17
data[2] => Mux~6.IN17
data[3] => Mux~0.IN16
data[3] => Mux~1.IN16
data[3] => Mux~2.IN16
data[3] => Mux~3.IN16
data[3] => Mux~4.IN16
data[3] => Mux~5.IN16
data[3] => Mux~6.IN16
dp => seg7led_bits~0.DATAA
reset => process0~0.IN0