iic.fit.eqn

VHDL基础的编程源代码

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--A1L32 is write_read~36 at LC123
A1L32_or_out = write_read;
A1L32 = A1L32_or_out;


--A1L33 is write_read~38 at LC125
A1L33_or_out = write_read;
A1L33 = A1L33_or_out;


--A1L34 is write_read~40 at LC115
A1L34_or_out = !write_read;
A1L34 = A1L34_or_out;


--A1L35 is write_read~42 at LC117
A1L35_or_out = !write_read;
A1L35 = A1L35_or_out;


--A1L36 is write_read~44 at LC120
A1L36_or_out = !write_read;
A1L36 = A1L36_or_out;


--A1L37 is write_read~46 at LC121
A1L37_or_out = write_read;
A1L37 = A1L37_or_out;


--B1_currentState[1] is iic_app:inst|currentState[1] at LC42
B1_currentState[1]_p1_out = !write_read & !B1_currentState[1] & !B1_currentState[0];
B1_currentState[1]_or_out = B1_currentState[1]_p1_out;
B1_currentState[1]_reg_input = !(B1_currentState[1]_or_out);
B1_currentState[1] = DFFE(B1_currentState[1]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--B1_currentState[0] is iic_app:inst|currentState[0] at LC30
B1_currentState[0]_p1_out = write_read & !B1_currentState[1] & !B1_currentState[0];
B1_currentState[0]_or_out = B1_currentState[0]_p1_out;
B1_currentState[0]_reg_input = !(B1_currentState[0]_or_out);
B1_currentState[0] = DFFE(B1_currentState[0]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--E1_delay_counter[0] is counter:inst3|delay_counter[0] at LC60
E1_delay_counter[0]_p1_out = !E1_delay_counter[4] & E1_delay_counter[3] & E1_delay_counter[2] & E1_delay_counter[1] & !E1_delay_counter[0];
E1_delay_counter[0]_or_out = E1_delay_counter[0]_p1_out;
E1_delay_counter[0]_reg_input = !E1_delay_counter[0]_or_out;
E1_delay_counter[0] = TFFE(E1_delay_counter[0]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--C1L8 is seg7_leddrv:inst1|seg7led_bits[7]~10 at LC113
C1L8_p1_out = !write_read & reset;
C1L8_or_out = C1L8_p1_out;
C1L8 = !(C1L8_or_out);


--B1_data_buffer[3] is iic_app:inst|data_buffer[3] at LC46
B1_data_buffer[3]_or_out = wr_data[3];
B1_data_buffer[3]_reg_input = B1_data_buffer[3]_or_out;
B1_data_buffer[3]_p3_out = reset & !B1_currentState[1] & !B1_currentState[0];
B1_data_buffer[3] = DFFE(B1_data_buffer[3]_reg_input, GLOBAL(clock_24M), , , B1_data_buffer[3]_p3_out);


--B1_data_buffer[2] is iic_app:inst|data_buffer[2] at LC48
B1_data_buffer[2]_or_out = wr_data[2];
B1_data_buffer[2]_reg_input = B1_data_buffer[2]_or_out;
B1_data_buffer[2]_p3_out = reset & !B1_currentState[1] & !B1_currentState[0];
B1_data_buffer[2] = DFFE(B1_data_buffer[2]_reg_input, GLOBAL(clock_24M), , , B1_data_buffer[2]_p3_out);


--B1_data_buffer[1] is iic_app:inst|data_buffer[1] at LC43
B1_data_buffer[1]_or_out = wr_data[1];
B1_data_buffer[1]_reg_input = B1_data_buffer[1]_or_out;
B1_data_buffer[1]_p3_out = reset & !B1_currentState[1] & !B1_currentState[0];
B1_data_buffer[1] = DFFE(B1_data_buffer[1]_reg_input, GLOBAL(clock_24M), , , B1_data_buffer[1]_p3_out);


--B1_data_buffer[0] is iic_app:inst|data_buffer[0] at LC20
B1_data_buffer[0]_or_out = wr_data[0];
B1_data_buffer[0]_reg_input = B1_data_buffer[0]_or_out;
B1_data_buffer[0]_p3_out = reset & !B1_currentState[1] & !B1_currentState[0];
B1_data_buffer[0] = DFFE(B1_data_buffer[0]_reg_input, GLOBAL(clock_24M), , , B1_data_buffer[0]_p3_out);


--B1_data_out[3] is iic_app:inst|data_out[3] at LC44
B1_data_out[3]_or_out = B1_data_buffer[3];
B1_data_out[3]_reg_input = B1_data_out[3]_or_out;
B1_data_out[3]_p3_out = !B1_currentState[1] & B1_currentState[0];
B1_data_out[3] = DFFE(B1_data_out[3]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , B1_data_out[3]_p3_out);


--B1_data_out[2] is iic_app:inst|data_out[2] at LC45
B1_data_out[2]_or_out = B1_data_buffer[2];
B1_data_out[2]_reg_input = B1_data_out[2]_or_out;
B1_data_out[2]_p3_out = !B1_currentState[1] & B1_currentState[0];
B1_data_out[2] = DFFE(B1_data_out[2]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , B1_data_out[2]_p3_out);


--B1_data_out[1] is iic_app:inst|data_out[1] at LC47
B1_data_out[1]_or_out = B1_data_buffer[1];
B1_data_out[1]_reg_input = B1_data_out[1]_or_out;
B1_data_out[1]_p3_out = !B1_currentState[1] & B1_currentState[0];
B1_data_out[1] = DFFE(B1_data_out[1]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , B1_data_out[1]_p3_out);


--B1_data_out[0] is iic_app:inst|data_out[0] at LC21
B1_data_out[0]_or_out = B1_data_buffer[0];
B1_data_out[0]_reg_input = B1_data_out[0]_or_out;
B1_data_out[0]_p3_out = !B1_currentState[1] & B1_currentState[0];
B1_data_out[0] = DFFE(B1_data_out[0]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , B1_data_out[0]_p3_out);


--E1_delay_counter[1] is counter:inst3|delay_counter[1] at LC63
E1_delay_counter[1]_p1_out = !E1_delay_counter[4] & E1_delay_counter[3] & E1_delay_counter[2] & E1_delay_counter[1];
E1_delay_counter[1]_or_out = E1_delay_counter[1]_p1_out # E1_delay_counter[0];
E1_delay_counter[1]_reg_input = E1_delay_counter[1]_or_out;
E1_delay_counter[1] = TFFE(E1_delay_counter[1]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--B1_data_write is iic_app:inst|data_write at LC28
B1_data_write_p1_out = B1_currentState[1] & !B1_currentState[0] & !B1_data_write;
B1_data_write_p2_out = !B1_currentState[1] & B1_currentState[0] & B1_data_write;
B1_data_write_or_out = B1_data_write_p1_out # B1_data_write_p2_out;
B1_data_write_reg_input = B1_data_write_or_out;
B1_data_write = TFFE(B1_data_write_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--B1_wr is iic_app:inst|wr at LC31
B1_wr_p1_out = !B1_currentState[1] & B1_currentState[0] & !B1_wr;
B1_wr_p2_out = B1_currentState[1] & B1_currentState[0] & B1_wr & D1_stop;
B1_wr_or_out = B1_wr_p1_out # B1_wr_p2_out;
B1_wr_reg_input = B1_wr_or_out;
B1_wr = TFFE(B1_wr_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--E1_delay_counter[2] is counter:inst3|delay_counter[2] at LC91
E1_delay_counter[2]_p1_out = !E1_delay_counter[4] & E1_delay_counter[3] & E1_delay_counter[1] & E1_delay_counter[2];
E1_delay_counter[2]_p2_out = E1_delay_counter[1] & E1_delay_counter[0];
E1_delay_counter[2]_or_out = E1_delay_counter[2]_p1_out # E1_delay_counter[2]_p2_out;
E1_delay_counter[2]_reg_input = E1_delay_counter[2]_or_out;
E1_delay_counter[2] = TFFE(E1_delay_counter[2]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--E1_delay_counter[3] is counter:inst3|delay_counter[3] at LC89
E1_delay_counter[3]_p1_out = !E1_delay_counter[4] & E1_delay_counter[2] & E1_delay_counter[1] & E1_delay_counter[3];
E1_delay_counter[3]_p2_out = E1_delay_counter[2] & E1_delay_counter[1] & E1_delay_counter[0];
E1_delay_counter[3]_or_out = E1_delay_counter[3]_p1_out # E1_delay_counter[3]_p2_out;
E1_delay_counter[3]_reg_input = E1_delay_counter[3]_or_out;
E1_delay_counter[3] = TFFE(E1_delay_counter[3]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--E1_delay_counter[4] is counter:inst3|delay_counter[4] at LC88
E1_delay_counter[4]_p1_out = E1_delay_counter[3] & E1_delay_counter[2] & E1_delay_counter[1] & E1_delay_counter[0];
E1_delay_counter[4]_or_out = E1_delay_counter[4];
E1_delay_counter[4]_reg_input = E1_delay_counter[4]_p1_out $ E1_delay_counter[4]_or_out;
E1_delay_counter[4] = DFFE(E1_delay_counter[4]_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , );


--E1_carrier is counter:inst3|carrier at LC81
E1_carrier_reg_input = VCC;
E1_carrier_p3_out = !E1_delay_counter[4] & E1_delay_counter[3] & E1_delay_counter[2] & E1_delay_counter[1] & !E1_delay_counter[0];
E1_carrier = TFFE(E1_carrier_reg_input, GLOBAL(clock_24M), GLOBAL(reset), , E1_carrier_p3_out);


--D1_scl is iic_controller:inst2|scl at LC5
D1_scl_reg_input = VCC;
D1_scl = TFFE(D1_scl_reg_input, E1_carrier, GLOBAL(reset), , );


--D1_send_devaddr_again_flag is iic_controller:inst2|send_devaddr_again_flag at LC67
D1_send_devaddr_again_flag_p1_out = !B1_wr & D1_scl & B1_rd & D1_currentState[1] & !D1_currentState[2] & !D1_currentState[3] & D1_currentState[0] & reset & !D1_send_devaddr_again_flag;