iic.map.rpt

VHDL基础的编程源代码

+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: iic_app:inst ;
+----------------+----------+-------------------------------+
; Parameter Name ; Value    ; Type                          ;
+----------------+----------+-------------------------------+
; device_addr    ; 10100000 ; Untyped                       ;
; memory_addr    ; 00000000 ; Untyped                       ;
+----------------+----------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: counter:inst3 ;
+---------------------+-------+------------------------------+
; Parameter Name      ; Value ; Type                         ;
+---------------------+-------+------------------------------+
; divisor             ; 30    ; Untyped                      ;
; inner_counter_width ; 4     ; Untyped                      ;
; unit                ; 1001  ; Untyped                      ;
+---------------------+-------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter:inst3|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+-----------------------------------------------+
; Parameter Name         ; Value       ; Type                                          ;
+------------------------+-------------+-----------------------------------------------+
; LPM_WIDTH              ; 5           ; Untyped                                       ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                       ;
; LPM_DIRECTION          ; ADD         ; Untyped                                       ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                       ;
; LPM_PIPELINE           ; 0           ; Untyped                                       ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                       ;
; REGISTERED_AT_END      ; 0           ; Untyped                                       ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                       ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                       ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                       ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                            ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                                       ;
; USE_WYS                ; OFF         ; Untyped                                       ;
; STYLE                  ; FAST        ; Untyped                                       ;
; CBXI_PARAMETER         ; add_sub_2nh ; Untyped                                       ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                    ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                  ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                  ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/03-源码文件/VHDL/15-IIC读写/iic.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Mar 27 11:40:24 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off iic -c iic
Info: Found 2 design units, including 1 entities, in source file seg7_leddrv.vhd
    Info: Found design unit 1: seg7_leddrv-seg7_leddrv_architecture
    Info: Found entity 1: seg7_leddrv
Info: Found 1 design units, including 1 entities, in source file iic.bdf
    Info: Found entity 1: iic
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-counter_architecture
    Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file iic_controller.vhd
    Info: Found design unit 1: iic_controller-iic_controller_architecture
    Info: Found entity 1: iic_controller
Info: Found 2 design units, including 1 entities, in source file iic_app.vhd
    Info: Found design unit 1: iic_app-iic_app_architecture
    Info: Found entity 1: iic_app
Info: Elaborating entity "iic" for the top level hierarchy
Warning: Port "rd" of type iic_app and instance "inst" is missing source signal
Warning: Port "wr" of type iic_app and instance "inst" is missing source signal
Warning: Port "carrier" of type counter and instance "inst3" is missing source signal
Warning: Port "counter" of type counter and instance "inst3" is missing source signal
Warning: Port "scl" of type iic_controller and instance "inst2" is missing source signal
Info: Elaborating entity "iic_controller" for hierarchy "iic_controller:inst2"
Info: Elaborating entity "iic_app" for hierarchy "iic_app:inst"
Warning (10030): Tied undriven net "data_buffer[7]" at iic_app.vhd(84) to X
Warning (10030): Tied undriven net "data_buffer[6]" at iic_app.vhd(84) to X
Warning (10030): Tied undriven net "data_buffer[5]" at iic_app.vhd(84) to X
Warning (10030): Tied undriven net "data_buffer[4]" at iic_app.vhd(84) to X
Info: Elaborating entity "counter" for hierarchy "counter:inst3"
Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "seg7_leddrv" for hierarchy "seg7_leddrv:inst1"
Info (10425): VHDL Case Statement information at seg7_leddrv.vhd(69): OTHERS choice is never selected
Warning: Reduced register "iic_app:inst|currentState[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|mem_addr[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|dev_addr[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|mem_addr[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|dev_addr[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|mem_addr[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|dev_addr[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|mem_addr[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|dev_addr[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|mem_addr[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|dev_addr[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|mem_addr[5]" with stuck data_in port to stuck value GND
Info: Power-up level of register "iic_app:inst|dev_addr[5]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "iic_app:inst|dev_addr[5]" with stuck data_in port to stuck value VCC
Warning: Reduced register "iic_app:inst|mem_addr[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|dev_addr[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|mem_addr[7]" with stuck data_in port to stuck value GND
Info: Power-up level of register "iic_app:inst|dev_addr[7]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "iic_app:inst|dev_addr[7]" with stuck data_in port to stuck value VCC
Warning: Reduced register "iic_app:inst|data_out[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|data_out[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|data_out[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "iic_app:inst|data_out[7]" with stuck data_in port to stuck value GND
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 6 buffer(s)
    Info: Ignored 6 SOFT buffer(s)
Warning: Converting TRI node "iic_app:inst|data_out_tmp~12" that feeds logic to an OR gate
Warning: Converting TRI node "iic_app:inst|data_out_tmp~16" that feeds logic to an OR gate
Warning: Converting TRI node "iic_app:inst|data_out_tmp~20" that feeds logic to an OR gate
Warning: Converting TRI node "iic_app:inst|data_out_tmp~24" that feeds logic to an OR gate
Warning: Converting TRI node "iic_controller:inst2|data_out_tmp~12" that feeds logic to an OR gate
Warning: Converting TRI node "iic_controller:inst2|data_out_tmp~16" that feeds logic to an OR gate
Warning: Converting TRI node "iic_controller:inst2|data_out_tmp~20" that feeds logic to an OR gate
Warning: Converting TRI node "iic_controller:inst2|data_out_tmp~24" that feeds logic to an OR gate
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock_24M" to global clock signal
    Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Implemented 130 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 15 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 107 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 39 warnings
    Info: Processing ended: Tue Mar 27 11:40:37 2007
    Info: Elapsed time: 00:00:14