iic.tan.rpt

VHDL基础的编程源代码

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM3128ATC100-10   ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock_24M       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock_24M'                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------+----------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                         ; To                                           ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------+----------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 26.18 MHz ( period = 38.200 ns )                    ; iic_controller:inst2|stop                    ; iic_app:inst|disp[0]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 7.700 ns                ;
; N/A                                     ; 27.03 MHz ( period = 37.000 ns )                    ; iic_controller:inst2|data_write              ; iic_app:inst|disp[0]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 27.03 MHz ( period = 37.000 ns )                    ; iic_controller:inst2|data_write              ; iic_app:inst|disp[3]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 27.03 MHz ( period = 37.000 ns )                    ; iic_controller:inst2|data_write              ; iic_app:inst|disp[1]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 27.03 MHz ( period = 37.000 ns )                    ; iic_controller:inst2|data_write              ; iic_app:inst|disp[2]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 27.47 MHz ( period = 36.400 ns )                    ; iic_controller:inst2|stop                    ; iic_app:inst|disp[3]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.800 ns                ;
; N/A                                     ; 27.47 MHz ( period = 36.400 ns )                    ; iic_controller:inst2|stop                    ; iic_app:inst|disp[1]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.800 ns                ;
; N/A                                     ; 27.47 MHz ( period = 36.400 ns )                    ; iic_controller:inst2|stop                    ; iic_app:inst|disp[2]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.800 ns                ;
; N/A                                     ; 27.62 MHz ( period = 36.200 ns )                    ; iic_controller:inst2|data_out[0]             ; iic_app:inst|disp[0]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 27.62 MHz ( period = 36.200 ns )                    ; iic_controller:inst2|data_out[3]             ; iic_app:inst|disp[3]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 27.62 MHz ( period = 36.200 ns )                    ; iic_controller:inst2|data_out[2]             ; iic_app:inst|disp[2]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 27.78 MHz ( period = 36.000 ns )                    ; iic_controller:inst2|data_out[1]             ; iic_app:inst|disp[1]                         ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.600 ns                ;
; N/A                                     ; 28.25 MHz ( period = 35.400 ns )                    ; iic_controller:inst2|scl                     ; iic_controller:inst2|sda_write               ; clock_24M  ; clock_24M ; None                        ; None                      ; 13.200 ns               ;
; N/A                                     ; 28.25 MHz ( period = 35.400 ns )                    ; iic_controller:inst2|scl                     ; iic_controller:inst2|sda_out                 ; clock_24M  ; clock_24M ; None                        ; None                      ; 13.200 ns               ;
; N/A                                     ; 28.90 MHz ( period = 34.600 ns )                    ; iic_controller:inst2|stop                    ; iic_app:inst|rd                              ; clock_24M  ; clock_24M ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 28.90 MHz ( period = 34.600 ns )                    ; iic_controller:inst2|stop                    ; iic_app:inst|wr                              ; clock_24M  ; clock_24M ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 40.00 MHz ( period = 25.000 ns )                    ; iic_controller:inst2|scl                     ; iic_controller:inst2|send_data[0]            ; clock_24M  ; clock_24M ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 40.00 MHz ( period = 25.000 ns )                    ; iic_controller:inst2|scl                     ; iic_controller:inst2|currentState[3]         ; clock_24M  ; clock_24M ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 40.00 MHz ( period = 25.000 ns )                    ; iic_controller:inst2|scl                     ; iic_controller:inst2|currentState[1]         ; clock_24M  ; clock_24M ; None                        ; None                      ; 8.000 ns                ;