keyboard1.map.rpt

VHDL基础的编程源代码

+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flip_latch:inst13 ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type                                  ;
+----------------+-------+---------------------------------------+
; data_width     ; 4     ; Untyped                               ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: counter:inst ;
+---------------------+-------+-----------------------------+
; Parameter Name      ; Value ; Type                        ;
+---------------------+-------+-----------------------------+
; divisor             ; 24000 ; Untyped                     ;
; inner_counter_width ; 15    ; Untyped                     ;
; unit                ; 1001  ; Untyped                     ;
+---------------------+-------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: delay_kbtingle:inst4|lpm_counter:currentState_rtl_0 ;
+------------------------+-------------------+---------------------------------------------------------+
; Parameter Name         ; Value             ; Type                                                    ;
+------------------------+-------------------+---------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                                              ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                                            ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                                            ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                                          ;
; LPM_WIDTH              ; 4                 ; Untyped                                                 ;
; LPM_DIRECTION          ; UP                ; Untyped                                                 ;
; LPM_MODULUS            ; 0                 ; Untyped                                                 ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                                 ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                                 ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                                 ;
; DEVICE_FAMILY          ; MAX3000A          ; Untyped                                                 ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                                 ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                                      ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                                      ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                                 ;
; LABWIDE_SCLR           ; ON                ; Untyped                                                 ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                                 ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                                 ;
+------------------------+-------------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/keyboard1.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 27 10:49:56 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keyboard1 -c keyboard1
Info: Found 2 design units, including 1 entities, in source file choice1from6.vhd
    Info: Found design unit 1: choice1from6-choice1from6_architecture
    Info: Found entity 1: choice1from6
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-counter_architecture
    Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file seg7_leddrv.vhd
    Info: Found design unit 1: seg7_leddrv-seg7_leddrv_architecture
    Info: Found entity 1: seg7_leddrv
Info: Found 2 design units, including 1 entities, in source file flip_latch.vhd
    Info: Found design unit 1: flip_latch-flip_latch_architecture
    Info: Found entity 1: flip_latch
Info: Found 2 design units, including 1 entities, in source file keyboard_scan.vhd
    Info: Found design unit 1: keyboard_scan-keyboard_scan_architecture
    Info: Found entity 1: keyboard_scan
Info: Found 2 design units, including 1 entities, in source file key_decode.vhd
    Info: Found design unit 1: key_decode-key_decode_architecture
    Info: Found entity 1: key_decode
Info: Found 2 design units, including 1 entities, in source file delay_kbtingle.vhd
    Info: Found design unit 1: delay_kbtingle-delay_kbtingle_architecture
    Info: Found entity 1: delay_kbtingle
Info: Found 1 design units, including 1 entities, in source file keyboard1.bdf
    Info: Found entity 1: keyboard1
Info: Elaborating entity "keyboard1" for the top level hierarchy
Warning: Port "carrier" of type counter and instance "inst1" is missing source signal
Warning: Port "counter" of type counter and instance "inst1" is missing source signal
Warning: Port "carrier" of type counter and instance "inst2" is missing source signal
Warning: Port "counter" of type counter and instance "inst2" is missing source signal
Warning: Port "led_cs" of type choice1from6 and instance "inst7" is missing source signal
Warning: Port "seg7led_bits" of type seg7_leddrv and instance "inst8" is missing source signal
Warning: Port "carrier" of type counter and instance "inst" is missing source signal
Warning: Port "counter" of type counter and instance "inst" is missing source signal
Info: Elaborating entity "delay_kbtingle" for hierarchy "delay_kbtingle:inst4"
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(76): signal "scan_start" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(79): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(80): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(90): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(96): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(102): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(117): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(118): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(119): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(120): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at delay_kbtingle.vhd(71): signal or variable "previous_row_data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "previous_row_data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at delay_kbtingle.vhd(71): signal or variable "key_data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "key_data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "counter" for hierarchy "counter:inst1"
Info: Elaborating entity "counter" for hierarchy "counter:inst2"
Info: Elaborating entity "keyboard_scan" for hierarchy "keyboard_scan:inst3"
Info: Elaborating entity "key_decode" for hierarchy "key_decode:inst5"
Info: Elaborating entity "choice1from6" for hierarchy "choice1from6:inst7"
Info: Elaborating entity "flip_latch" for hierarchy "flip_latch:inst6"
Info: Elaborating entity "seg7_leddrv" for hierarchy "seg7_leddrv:inst8"
Info (10425): VHDL Case Statement information at seg7_leddrv.vhd(69): OTHERS choice is never selected
Info: Elaborating entity "counter" for hierarchy "counter:inst"
Info: Power-up level of register "choice1from6:inst7|dp" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "choice1from6:inst7|dp" with stuck data_in port to stuck value VCC
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "delay_kbtingle:inst4|currentState[0]~0"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_constant.tdf
    Info: Found entity 1: lpm_constant
Info: Ignored 5 buffer(s)
    Info: Ignored 5 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "seg7led_bits[7]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clear signal driven by pin "reset" to global clear signal
    Info: Promoted clock signal driven by pin "clock_1k" to global clock signal
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "clock"
Info: Implemented 160 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 31 output pins
    Info: Implemented 113 macrocells
    Info: Implemented 9 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Processing ended: Fri Apr 27 10:50:14 2007
    Info: Elapsed time: 00:00:19