digital6counter.tan.qmsg

VHDL基础的编程源代码

{ "Info" "ITDB_FULL_TPD_RESULT" "reset seg7led_bits\[0\] 10.200 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"seg7led_bits\[0\]\" is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 113 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 113; PIN Node = 'reset'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "" { reset } "NODE_NAME" } "" } } { "DigitalClock.bdf" "" { Schematic "H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf" { { -48 -8 160 -32 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(4.400 ns) 8.600 ns seg7_leddrv:inst9\|Mux~1275 2 COMB LC115 1 " "Info: 2: + IC(1.700 ns) + CELL(4.400 ns) = 8.600 ns; Loc. = LC115; Fanout = 1; COMB Node = 'seg7_leddrv:inst9\|Mux~1275'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.100 ns" { reset seg7_leddrv:inst9|Mux~1275 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.200 ns seg7led_bits\[0\] 3 PIN PIN_76 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.200 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'seg7led_bits\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "1.600 ns" { seg7_leddrv:inst9|Mux~1275 seg7led_bits[0] } "NODE_NAME" } "" } } { "DigitalClock.bdf" "" { Schematic "H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf" { { 296 1208 1390 312 "seg7led_bits\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 83.33 % ) " "Info: Total cell delay = 8.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.700 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "10.200 ns" { reset seg7_leddrv:inst9|Mux~1275 seg7led_bits[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.200 ns" { reset reset~out seg7_leddrv:inst9|Mux~1275 seg7led_bits[0] } { 0.000ns 0.000ns 1.700ns 0.000ns } { 0.000ns 2.500ns 4.400ns 1.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 24 23:23:54 2007 " "Info: Processing ended: Sat Mar 24 23:23:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}