digital6counter.tan.qmsg

VHDL基础的编程源代码

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf" { { -64 -8 160 -48 "clock" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter:inst7\|carrier " "Info: Detected ripple clock \"counter:inst7\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst7\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst5\|carrier " "Info: Detected ripple clock \"counter:inst5\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst5\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst4\|carrier " "Info: Detected ripple clock \"counter:inst4\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst4\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst3\|carrier " "Info: Detected ripple clock \"counter:inst3\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst3\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst2\|carrier " "Info: Detected ripple clock \"counter:inst2\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst2\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst1\|carrier " "Info: Detected ripple clock \"counter:inst1\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst1\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst11\|carrier " "Info: Detected ripple clock \"counter:inst11\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst11\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst\|carrier " "Info: Detected ripple clock \"counter:inst\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register counter:inst6\|counter\[1\] register choice1from6:inst8\|led_bits\[1\] 17.67 MHz 56.6 ns Internal " "Info: Clock \"clock\" has Internal fmax of 17.67 MHz between source register \"counter:inst6\|counter\[1\]\" and destination register \"choice1from6:inst8\|led_bits\[1\]\" (period= 56.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Longest register register " "Info: + Longest register to register delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst6\|counter\[1\] 1 REG LC41 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC41; Fanout = 6; REG Node = 'counter:inst6\|counter\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "" { counter:inst6|counter[1] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 4.000 ns choice1from6:inst8\|Mux~3900 2 COMB LC6 1 " "Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 4.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'choice1from6:inst8\|Mux~3900'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "4.000 ns" { counter:inst6|counter[1] choice1from6:inst8|Mux~3900 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 6.700 ns choice1from6:inst8\|led_bits\[1\] 3 REG LC7 21 " "Info: 3: + IC(0.000 ns) + CELL(2.700 ns) = 6.700 ns; Loc. = LC7; Fanout = 21; REG Node = 'choice1from6:inst8\|led_bits\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "2.700 ns" { choice1from6:inst8|Mux~3900 choice1from6:inst8|led_bits[1] } "NODE_NAME" } "" } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/choice1from6.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 59.70 % ) " "Info: Total cell delay = 4.000 ns ( 59.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 40.30 % ) " "Info: Total interconnect delay = 2.700 ns ( 40.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.700 ns" { counter:inst6|counter[1] choice1from6:inst8|Mux~3900 choice1from6:inst8|led_bits[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { counter:inst6|counter[1] choice1from6:inst8|Mux~3900 choice1from6:inst8|led_bits[1] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 1.300ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-45.400 ns - Smallest " "Info: - Smallest clock skew is -45.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 16 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 16; CLK Node = 'clock'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "" { clock } "NODE_NAME" } "" } } { "DigitalClock.bdf" "" { Schematic "H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf" { { -64 -8 160 -48 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst\|carrier 2 REG LC19 26 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC19; Fanout = 26; REG Node = 'counter:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "2.500 ns" { clock counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 10.000 ns choice1from6:inst8\|led_bits\[1\] 3 REG LC7 21 " "Info: 3: + IC(2.800 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC7; Fanout = 21; REG Node = 'choice1from6:inst8\|led_bits\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "5.000 ns" { counter:inst|carrier choice1from6:inst8|led_bits[1] } "NODE_NAME" } "" } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/choice1from6.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total cell delay = 7.200 ns ( 72.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 28.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "10.000 ns" { clock counter:inst|carrier choice1from6:inst8|led_bits[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock clock~out counter:inst|carrier choice1from6:inst8|led_bits[1] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 55.400 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 55.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 16 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 16; CLK Node = 'clock'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "" { clock } "NODE_NAME" } "" } } { "DigitalClock.bdf" "" { Schematic "H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf" { { -64 -8 160 -48 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst\|carrier 2 REG LC19 26 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC19; Fanout = 26; REG Node = 'counter:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "2.500 ns" { clock counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.800 ns) 11.600 ns counter:inst11\|carrier 3 REG LC50 10 " "Info: 3: + IC(2.800 ns) + CELL(3.800 ns) = 11.600 ns; Loc. = LC50; Fanout = 10; REG Node = 'counter:inst11\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.600 ns" { counter:inst|carrier counter:inst11|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 18.100 ns counter:inst1\|carrier 4 REG LC49 10 " "Info: 4: + IC(2.700 ns) + CELL(3.800 ns) = 18.100 ns; Loc. = LC49; Fanout = 10; REG Node = 'counter:inst1\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.500 ns" { counter:inst11|carrier counter:inst1|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 24.600 ns counter:inst2\|carrier 5 REG LC68 9 " "Info: 5: + IC(2.700 ns) + CELL(3.800 ns) = 24.600 ns; Loc. = LC68; Fanout = 9; REG Node = 'counter:inst2\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.500 ns" { counter:inst1|carrier counter:inst2|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 31.100 ns counter:inst3\|carrier 6 REG LC96 10 " "Info: 6: + IC(2.700 ns) + CELL(3.800 ns) = 31.100 ns; Loc. = LC96; Fanout = 10; REG Node = 'counter:inst3\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.500 ns" { counter:inst2|carrier counter:inst3|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 37.600 ns counter:inst4\|carrier 7 REG LC97 9 " "Info: 7: + IC(2.700 ns) + CELL(3.800 ns) = 37.600 ns; Loc. = LC97; Fanout = 9; REG Node = 'counter:inst4\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.500 ns" { counter:inst3|carrier counter:inst4|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 44.100 ns counter:inst5\|carrier 8 REG LC65 10 " "Info: 8: + IC(2.700 ns) + CELL(3.800 ns) = 44.100 ns; Loc. = LC65; Fanout = 10; REG Node = 'counter:inst5\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.500 ns" { counter:inst4|carrier counter:inst5|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 50.600 ns counter:inst7\|carrier 9 REG LC77 5 " "Info: 9: + IC(2.700 ns) + CELL(3.800 ns) = 50.600 ns; Loc. = LC77; Fanout = 5; REG Node = 'counter:inst7\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.500 ns" { counter:inst5|carrier counter:inst7|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.200 ns) 55.400 ns counter:inst6\|counter\[1\] 10 REG LC41 6 " "Info: 10: + IC(2.600 ns) + CELL(2.200 ns) = 55.400 ns; Loc. = LC41; Fanout = 6; REG Node = 'counter:inst6\|counter\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "4.800 ns" { counter:inst7|carrier counter:inst6|counter[1] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "33.800 ns ( 61.01 % ) " "Info: Total cell delay = 33.800 ns ( 61.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "21.600 ns ( 38.99 % ) " "Info: Total interconnect delay = 21.600 ns ( 38.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "55.400 ns" { clock counter:inst|carrier counter:inst11|carrier counter:inst1|carrier counter:inst2|carrier counter:inst3|carrier counter:inst4|carrier counter:inst5|carrier counter:inst7|carrier counter:inst6|counter[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "55.400 ns" { clock clock~out counter:inst|carrier counter:inst11|carrier counter:inst1|carrier counter:inst2|carrier counter:inst3|carrier counter:inst4|carrier counter:inst5|carrier counter:inst7|carrier counter:inst6|counter[1] } { 0.000ns 0.000ns 0.000ns 2.800ns 2.700ns 2.700ns 2.700ns 2.700ns 2.700ns 2.700ns 2.600ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "10.000 ns" { clock counter:inst|carrier choice1from6:inst8|led_bits[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock clock~out counter:inst|carrier choice1from6:inst8|led_bits[1] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "55.400 ns" { clock counter:inst|carrier counter:inst11|carrier counter:inst1|carrier counter:inst2|carrier counter:inst3|carrier counter:inst4|carrier counter:inst5|carrier counter:inst7|carrier counter:inst6|counter[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "55.400 ns" { clock clock~out counter:inst|carrier counter:inst11|carrier counter:inst1|carrier counter:inst2|carrier counter:inst3|carrier counter:inst4|carrier counter:inst5|carrier counter:inst7|carrier counter:inst6|counter[1] } { 0.000ns 0.000ns 0.000ns 2.800ns 2.700ns 2.700ns 2.700ns 2.700ns 2.700ns 2.700ns 2.600ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/choice1from6.vhd" 79 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.700 ns" { counter:inst6|counter[1] choice1from6:inst8|Mux~3900 choice1from6:inst8|led_bits[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { counter:inst6|counter[1] choice1from6:inst8|Mux~3900 choice1from6:inst8|led_bits[1] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 1.300ns 2.700ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "10.000 ns" { clock counter:inst|carrier choice1from6:inst8|led_bits[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock clock~out counter:inst|carrier choice1from6:inst8|led_bits[1] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "55.400 ns" { clock counter:inst|carrier counter:inst11|carrier counter:inst1|carrier counter:inst2|carrier counter:inst3|carrier counter:inst4|carrier counter:inst5|carrier counter:inst7|carrier counter:inst6|counter[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "55.400 ns" { clock clock~out counter:inst|carrier counter:inst11|carrier counter:inst1|carrier counter:inst2|carrier counter:inst3|carrier counter:inst4|carrier counter:inst5|carrier counter:inst7|carrier counter:inst6|counter[1] } { 0.000ns 0.000ns 0.000ns 2.800ns 2.700ns 2.700ns 2.700ns 2.700ns 2.700ns 2.700ns 2.600ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 3.800ns 2.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock led_bits\[5\] counter:inst1\|counter\[1\] 26.800 ns register " "Info: tco from clock \"clock\" to destination pin \"led_bits\[5\]\" through register \"counter:inst1\|counter\[1\]\" is 26.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 16.500 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 16.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock 1 CLK PIN_87 16 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 16; CLK Node = 'clock'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "" { clock } "NODE_NAME" } "" } } { "DigitalClock.bdf" "" { Schematic "H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf" { { -64 -8 160 -48 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst\|carrier 2 REG LC19 26 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC19; Fanout = 26; REG Node = 'counter:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "2.500 ns" { clock counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.800 ns) 11.600 ns counter:inst11\|carrier 3 REG LC50 10 " "Info: 3: + IC(2.800 ns) + CELL(3.800 ns) = 11.600 ns; Loc. = LC50; Fanout = 10; REG Node = 'counter:inst11\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "6.600 ns" { counter:inst|carrier counter:inst11|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 16.500 ns counter:inst1\|counter\[1\] 4 REG LC98 17 " "Info: 4: + IC(2.700 ns) + CELL(2.200 ns) = 16.500 ns; Loc. = LC98; Fanout = 17; REG Node = 'counter:inst1\|counter\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "4.900 ns" { counter:inst11|carrier counter:inst1|counter[1] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 66.67 % ) " "Info: Total cell delay = 11.000 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns ( 33.33 % ) " "Info: Total interconnect delay = 5.500 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "16.500 ns" { clock counter:inst|carrier counter:inst11|carrier counter:inst1|counter[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.500 ns" { clock clock~out counter:inst|carrier counter:inst11|carrier counter:inst1|counter[1] } { 0.000ns 0.000ns 0.000ns 2.800ns 2.700ns } { 0.000ns 2.500ns 2.500ns 3.800ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest register pin " "Info: + Longest register to pin delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst1\|counter\[1\] 1 REG LC98 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC98; Fanout = 17; REG Node = 'counter:inst1\|counter\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "" { counter:inst1|counter[1] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/03-数字钟/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 7.100 ns leddrv:inst10\|Mux~530 2 COMB LC109 1 " "Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 7.100 ns; Loc. = LC109; Fanout = 1; COMB Node = 'leddrv:inst10\|Mux~530'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "7.100 ns" { counter:inst1|counter[1] leddrv:inst10|Mux~530 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 8.700 ns led_bits\[5\] 3 PIN PIN_71 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.700 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'led_bits\[5\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "1.600 ns" { leddrv:inst10|Mux~530 led_bits[5] } "NODE_NAME" } "" } } { "DigitalClock.bdf" "" { Schematic "H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf" { { 144 1208 1390 160 "led_bits\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 68.97 % ) " "Info: Total cell delay = 6.000 ns ( 68.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 31.03 % ) " "Info: Total interconnect delay = 2.700 ns ( 31.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "8.700 ns" { counter:inst1|counter[1] leddrv:inst10|Mux~530 led_bits[5] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.700 ns" { counter:inst1|counter[1] leddrv:inst10|Mux~530 led_bits[5] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "16.500 ns" { clock counter:inst|carrier counter:inst11|carrier counter:inst1|counter[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.500 ns" { clock clock~out counter:inst|carrier counter:inst11|carrier counter:inst1|counter[1] } { 0.000ns 0.000ns 0.000ns 2.800ns 2.700ns } { 0.000ns 2.500ns 2.500ns 3.800ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Digital6Counter" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/03-数字钟/db/Digital6Counter.quartus_db" { Floorplan "H:/03-源码文件/VHDL/03-数字钟/" "" "8.700 ns" { counter:inst1|counter[1] leddrv:inst10|Mux~530 led_bits[5] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.700 ns" { counter:inst1|counter[1] leddrv:inst10|Mux~530 led_bits[5] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}