keyboard1.map.rpt

VHDL基础的编程源代码

; LABWIDE_SCLR           ; ON                ; Untyped                                                 ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                                 ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                                 ;
+------------------------+-------------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter:inst|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name         ; Value       ; Type                                         ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH              ; 15          ; Untyped                                      ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                      ;
; LPM_DIRECTION          ; ADD         ; Untyped                                      ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                      ;
; LPM_PIPELINE           ; 0           ; Untyped                                      ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                      ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                           ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                                      ;
; USE_WYS                ; OFF         ; Untyped                                      ;
; STYLE                  ; FAST        ; Untyped                                      ;
; CBXI_PARAMETER         ; add_sub_joh ; Untyped                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                               ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in U:/02-开发板/CA328/03-源码文件/VHDL/06-键盘阵列-LED点阵显示/keyboard1.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 27 11:49:04 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keyboard1 -c keyboard1
Info: Found 2 design units, including 1 entities, in source file charlib8_8.vhd
    Info: Found design unit 1: charlib8_8-charlib8_8_architecture
    Info: Found entity 1: charlib8_8
Info: Found 2 design units, including 1 entities, in source file ledarray_drv.vhd
    Info: Found design unit 1: ledarray_drv-ledarray_drv_architecture
    Info: Found entity 1: ledarray_drv
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-counter_architecture
    Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file keyboard_scan.vhd
    Info: Found design unit 1: keyboard_scan-keyboard_scan_architecture
    Info: Found entity 1: keyboard_scan
Info: Found 2 design units, including 1 entities, in source file key_decode.vhd
    Info: Found design unit 1: key_decode-key_decode_architecture
    Info: Found entity 1: key_decode
Info: Found 2 design units, including 1 entities, in source file delay_kbtingle.vhd
    Info: Found design unit 1: delay_kbtingle-delay_kbtingle_architecture
    Info: Found entity 1: delay_kbtingle
Info: Found 1 design units, including 1 entities, in source file keyboard1.bdf
    Info: Found entity 1: keyboard1
Info: Elaborating entity "keyboard1" for the top level hierarchy
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Port "carrier" of type counter and instance "inst" is missing source signal
Warning: Port "counter" of type counter and instance "inst" is missing source signal
Warning: Port "carrier" of type counter and instance "inst1" is missing source signal
Warning: Port "counter" of type counter and instance "inst1" is missing source signal
Warning: Port "carrier" of type counter and instance "inst2" is missing source signal
Warning: Port "counter" of type counter and instance "inst2" is missing source signal
Info: Elaborating entity "ledarray_drv" for hierarchy "ledarray_drv:inst8"
Info: Elaborating entity "counter" for hierarchy "counter:inst"
Info: Elaborating entity "charlib8_8" for hierarchy "charlib8_8:inst7"
Info: Elaborating entity "key_decode" for hierarchy "key_decode:inst5"
Info: Elaborating entity "delay_kbtingle" for hierarchy "delay_kbtingle:inst4"
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(72): signal "scan_start" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(75): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(76): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(86): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(92): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(98): signal "row_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(113): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(114): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(115): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at delay_kbtingle.vhd(116): signal "row_select" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at delay_kbtingle.vhd(67): signal or variable "previous_row_data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "previous_row_data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at delay_kbtingle.vhd(67): signal or variable "key_data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "key_data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "counter" for hierarchy "counter:inst1"
Info: Elaborating entity "counter" for hierarchy "counter:inst2"
Info: Elaborating entity "keyboard_scan" for hierarchy "keyboard_scan:inst3"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "delay_kbtingle:inst4|currentState[0]~0"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_constant.tdf
    Info: Found entity 1: lpm_constant
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Ignored 20 buffer(s)
    Info: Ignored 20 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register "ledarray_drv:inst8|row[0]" merged to single register "ledarray_drv:inst8|row[7]"
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock" to global clock signal
    Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clear signal driven by pin "reset" to global clear signal
    Info: Promoted clock signal driven by pin "clock" to global clock signal
Info: Implemented 170 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 20 output pins
    Info: Implemented 114 macrocells
    Info: Implemented 30 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings
    Info: Processing ended: Fri Apr 27 11:49:29 2007
    Info: Elapsed time: 00:00:26