📄 ledarray8_8.map.rpt
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Analysis & Synthesis report for LedArray8_8
Sun Mar 25 00:17:14 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Parameter Settings for User Entity Instance: counter:inst
8. Parameter Settings for User Entity Instance: charlib8_8:inst6
9. Parameter Settings for User Entity Instance: bcd_ascii:inst2
10. Parameter Settings for User Entity Instance: choice1from2:inst1
11. Parameter Settings for User Entity Instance: counter:inst4
12. Parameter Settings for User Entity Instance: counter:inst3
13. Parameter Settings for User Entity Instance: counter:inst5
14. Parameter Settings for Inferred Entity Instance: counter:inst|lpm_add_sub:add_rtl_0
15. Parameter Settings for Inferred Entity Instance: counter:inst3|lpm_add_sub:add_rtl_1
16. Analysis & Synthesis Equations
17. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Mar 25 00:17:14 2007 ;
; Quartus II Version ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name ; LedArray8_8 ;
; Top-level Entity Name ; LedArray8_8 ;
; Family ; MAX3000A ;
; Total macrocells ; 117 ;
; Total pins ; 20 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device ; EPM3128ATC100-10 ; ;
; Top-level entity name ; LedArray8_8 ; LedArray8_8 ;
; Family name ; MAX3000A ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
+----------------------------------------------------------------------+------------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; bcd_ascii.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/04-LED点阵动态扫描显示/bcd_ascii.vhd ;
; counter.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/04-LED点阵动态扫描显示/counter.vhd ;
; LedArray8_8.bdf ; yes ; User Block Diagram/Schematic File ; H:/03-源码文件/VHDL/04-LED点阵动态扫描显示/LedArray8_8.bdf ;
; choice1from2.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/04-LED点阵动态扫描显示/choice1from2.vhd ;
; charlib8_8.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/04-LED点阵动态扫描显示/charlib8_8.vhd ;
; ledarray_drv.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/04-LED点阵动态扫描显示/ledarray_drv.vhd ;
; lpm_add_sub.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal51.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/aglobal51.inc ;
; addcore.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf ;
; look_add.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/look_add.tdf ;
; altshift.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/altshift.tdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 117 ;
; Total registers ; 59 ;
; I/O pins ; 20 ;
; Shareable expanders ; 13 ;
; Parallel expanders ; 21 ;
; Maximum fan-out node ; reset ;
; Maximum fan-out ; 63 ;
; Total fan-out ; 1004 ;
; Average fan-out ; 6.69 ;
+----------------------+----------------------+
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------------------+
; |LedArray8_8 ; 117 ; 20 ; |LedArray8_8 ;
; |counter:inst3| ; 8 ; 0 ; |LedArray8_8|counter:inst3 ;
; |counter:inst4| ; 9 ; 0 ; |LedArray8_8|counter:inst4 ;
; |counter:inst5| ; 4 ; 0 ; |LedArray8_8|counter:inst5 ;
; |counter:inst| ; 17 ; 0 ; |LedArray8_8|counter:inst ;
; |ledarray_drv:inst7| ; 77 ; 0 ; |LedArray8_8|ledarray_drv:inst7 ;
+----------------------------+------------+------+---------------------------------+
+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: counter:inst ;
+---------------------+-------+-----------------------------+
; Parameter Name ; Value ; Type ;
+---------------------+-------+-----------------------------+
; divisor ; 24000 ; Untyped ;
; inner_counter_width ; 16 ; Untyped ;
; unit ; 1001 ; Untyped ;
+---------------------+-------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: charlib8_8:inst6 ;
+----------------+-------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------+
; element_count ; 10 ; Untyped ;
+----------------+-------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: bcd_ascii:inst2 ;
+----------------+-------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------+
; data_width ; 4 ; Untyped ;
+----------------+-------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: choice1from2:inst1 ;
+----------------+-------+----------------------------------------+
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