flowingled.tan.qmsg

VHDL基础的编程源代码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter:inst\|carrier " "Info: Detected ripple clock \"counter:inst\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 51 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register counter:inst\|delay_counter\[0\] register counter:inst\|delay_counter\[8\] 89.29 MHz 11.2 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 89.29 MHz between source register \"counter:inst\|delay_counter\[0\]\" and destination register \"counter:inst\|delay_counter\[8\]\" (period= 11.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Longest register register " "Info: + Longest register to register delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst\|delay_counter\[0\] 1 REG LC18 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 37; REG Node = 'counter:inst\|delay_counter\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "" { counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 4.000 ns counter:inst\|delay_counter~161 2 COMB LC1 1 " "Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 4.000 ns; Loc. = LC1; Fanout = 1; COMB Node = 'counter:inst\|delay_counter~161'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "4.000 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~161 } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 6.700 ns counter:inst\|delay_counter\[8\] 3 REG LC2 34 " "Info: 3: + IC(0.000 ns) + CELL(2.700 ns) = 6.700 ns; Loc. = LC2; Fanout = 34; REG Node = 'counter:inst\|delay_counter\[8\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "2.700 ns" { counter:inst|delay_counter~161 counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 59.70 % ) " "Info: Total cell delay = 4.000 ns ( 59.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 40.30 % ) " "Info: Total interconnect delay = 2.700 ns ( 40.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "6.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~161 counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~161 counter:inst|delay_counter[8] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 1.300ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 26 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 26; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "" { clock_24M } "NODE_NAME" } "" } } { "FlowingLed.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/FlowingLed.bdf" { { 128 40 208 144 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter:inst\|delay_counter\[8\] 2 REG LC2 34 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 34; REG Node = 'counter:inst\|delay_counter\[8\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "0.900 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "3.400 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 26 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 26; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "" { clock_24M } "NODE_NAME" } "" } } { "FlowingLed.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/FlowingLed.bdf" { { 128 40 208 144 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter:inst\|delay_counter\[0\] 2 REG LC18 37 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC18; Fanout = 37; REG Node = 'counter:inst\|delay_counter\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "0.900 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "3.400 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "3.400 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "3.400 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "6.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~161 counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~161 counter:inst|delay_counter[8] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 1.300ns 2.700ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "3.400 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "3.400 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M led_bits\[4\] counter:inst6\|lpm_counter:counter_rtl_0\|dffs\[0\] 20.200 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"led_bits\[4\]\" through register \"counter:inst6\|lpm_counter:counter_rtl_0\|dffs\[0\]\" is 20.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 9.800 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 26 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 26; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "" { clock_24M } "NODE_NAME" } "" } } { "FlowingLed.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/FlowingLed.bdf" { { 128 40 208 144 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst\|carrier 2 REG LC9 5 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC9; Fanout = 5; REG Node = 'counter:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "2.500 ns" { clock_24M counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.200 ns) 9.800 ns counter:inst6\|lpm_counter:counter_rtl_0\|dffs\[0\] 3 REG LC20 28 " "Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC20; Fanout = 28; REG Node = 'counter:inst6\|lpm_counter:counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "4.800 ns" { counter:inst|carrier counter:inst6|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 73.47 % ) " "Info: Total cell delay = 7.200 ns ( 73.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 26.53 % ) " "Info: Total interconnect delay = 2.600 ns ( 26.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "9.800 ns" { clock_24M counter:inst|carrier counter:inst6|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.800 ns" { clock_24M clock_24M~out counter:inst|carrier counter:inst6|lpm_counter:counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.800 ns + Longest register pin " "Info: + Longest register to pin delay is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst6\|lpm_counter:counter_rtl_0\|dffs\[0\] 1 REG LC20 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC20; Fanout = 28; REG Node = 'counter:inst6\|lpm_counter:counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "" { counter:inst6|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(4.400 ns) 7.200 ns leddrv:inst4\|Mux~1044 2 COMB LC107 1 " "Info: 2: + IC(2.800 ns) + CELL(4.400 ns) = 7.200 ns; Loc. = LC107; Fanout = 1; COMB Node = 'leddrv:inst4\|Mux~1044'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "7.200 ns" { counter:inst6|lpm_counter:counter_rtl_0|dffs[0] leddrv:inst4|Mux~1044 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 8.800 ns led_bits\[4\] 3 PIN PIN_70 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.800 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'led_bits\[4\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "1.600 ns" { leddrv:inst4|Mux~1044 led_bits[4] } "NODE_NAME" } "" } } { "FlowingLed.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/FlowingLed.bdf" { { 304 744 920 320 "led_bits\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 68.18 % ) " "Info: Total cell delay = 6.000 ns ( 68.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 31.82 % ) " "Info: Total interconnect delay = 2.800 ns ( 31.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "8.800 ns" { counter:inst6|lpm_counter:counter_rtl_0|dffs[0] leddrv:inst4|Mux~1044 led_bits[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.800 ns" { counter:inst6|lpm_counter:counter_rtl_0|dffs[0] leddrv:inst4|Mux~1044 led_bits[4] } { 0.000ns 2.800ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "9.800 ns" { clock_24M counter:inst|carrier counter:inst6|lpm_counter:counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.800 ns" { clock_24M clock_24M~out counter:inst|carrier counter:inst6|lpm_counter:counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns 2.600ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "8.800 ns" { counter:inst6|lpm_counter:counter_rtl_0|dffs[0] leddrv:inst4|Mux~1044 led_bits[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.800 ns" { counter:inst6|lpm_counter:counter_rtl_0|dffs[0] leddrv:inst4|Mux~1044 led_bits[4] } { 0.000ns 2.800ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset led_bits\[4\] 10.100 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"led_bits\[4\]\" is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 49 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 49; PIN Node = 'reset'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "" { reset } "NODE_NAME" } "" } } { "FlowingLed.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/FlowingLed.bdf" { { 144 40 208 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(4.400 ns) 8.500 ns leddrv:inst4\|Mux~1044 2 COMB LC107 1 " "Info: 2: + IC(1.600 ns) + CELL(4.400 ns) = 8.500 ns; Loc. = LC107; Fanout = 1; COMB Node = 'leddrv:inst4\|Mux~1044'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "6.000 ns" { reset leddrv:inst4|Mux~1044 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.100 ns led_bits\[4\] 3 PIN PIN_70 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.100 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'led_bits\[4\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "1.600 ns" { leddrv:inst4|Mux~1044 led_bits[4] } "NODE_NAME" } "" } } { "FlowingLed.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/FlowingLed.bdf" { { 304 744 920 320 "led_bits\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 84.16 % ) " "Info: Total cell delay = 8.500 ns ( 84.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 15.84 % ) " "Info: Total interconnect delay = 1.600 ns ( 15.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FlowingLed" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/db/FlowingLed.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/01-流水灯/" "" "10.100 ns" { reset leddrv:inst4|Mux~1044 led_bits[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { reset reset~out leddrv:inst4|Mux~1044 led_bits[4] } { 0.000ns 0.000ns 1.600ns 0.000ns } { 0.000ns 2.500ns 4.400ns 1.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 27 09:29:54 2007 " "Info: Processing ended: Fri Apr 27 09:29:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}