flowingled.tan.rpt

来自「VHDL基础的编程源代码」· RPT 代码 · 共 274 行 · 第 1/5 页

; Device Name                                           ; EPM3128ATC100-10   ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock_24M       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock_24M'                                                                                                                                                                                                                                                                                       ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                            ; To                                              ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[0]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[1]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[2]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[3]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[4]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[5]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[6]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[7]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[8]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[14]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[13]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[12]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[10]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[9]                   ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; counter:inst|delay_counter[11]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; counter:inst|delay_counter[24]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.600 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; counter:inst|delay_counter[23]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.600 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; counter:inst|delay_counter[22]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.600 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; counter:inst|delay_counter[21]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.600 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; counter:inst|delay_counter[19]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.600 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; counter:inst|delay_counter[18]                  ; counter:inst|delay_counter[8]                   ; clock_24M  ; clock_24M ; None                        ; None                      ; 6.600 ns                ;