digital6counter.map.qmsg

VHDL基础的编程源代码

{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst6 " "Warning: Port \"counter\" of type counter and instance \"inst6\" is missing source signal" {  } { { "Digital6Counter.bdf" "" { Schematic "H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.bdf" { { 872 192 336 968 "inst6" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "leddrv leddrv:inst10 " "Info: Elaborating entity \"leddrv\" for hierarchy \"leddrv:inst10\"" {  } { { "Digital6Counter.bdf" "inst10" { Schematic "H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.bdf" { { 120 976 1144 216 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst2 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst2\"" {  } { { "Digital6Counter.bdf" "inst2" { Schematic "H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.bdf" { { 272 192 336 368 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset counter.vhd(63) " "Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst1 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst1\"" {  } { { "Digital6Counter.bdf" "inst1" { Schematic "H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.bdf" { { 152 192 336 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset counter.vhd(63) " "Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst\"" {  } { { "Digital6Counter.bdf" "inst" { Schematic "H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.bdf" { { 24 192 336 120 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset counter.vhd(63) " "Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "choice1from6 choice1from6:inst8 " "Info: Elaborating entity \"choice1from6\" for hierarchy \"choice1from6:inst8\"" {  } { { "Digital6Counter.bdf" "inst8" { Schematic "H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.bdf" { { 272 584 864 464 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7_leddrv seg7_leddrv:inst9 " "Info: Elaborating entity \"seg7_leddrv\" for hierarchy \"seg7_leddrv:inst9\"" {  } { { "Digital6Counter.bdf" "inst9" { Schematic "H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.bdf" { { 272 976 1168 368 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "seg7_leddrv.vhd(69) " "Info (10425): VHDL Case Statement information at seg7_leddrv.vhd(69): OTHERS choice is never selected" {  } { { "seg7_leddrv.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/seg7_leddrv.vhd" 69 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "23 " "Info: Ignored 23 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "23 " "Info: Ignored 23 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "choice1from6:inst8\|dp choice1from6:inst8\|led_cs\[1\] " "Info: Duplicate register \"choice1from6:inst8\|dp\" merged to single register \"choice1from6:inst8\|led_cs\[1\]\"" {  } { { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 53 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 51 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 51 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "choice1from6.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/choice1from6.vhd" 79 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 51 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 51 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 51 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 51 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/02-6位十进制计数器/counter.vhd" 51 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin \"clock\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "135 " "Info: Implemented 135 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "22 " "Info: Implemented 22 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "111 " "Info: Implemented 111 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 24 22:44:18 2007 " "Info: Processing ended: Sat Mar 24 22:44:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}