📄 digital6counter.map.rpt
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; Parameter Settings for Inferred Entity Instance: counter:inst1|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-----------------------------------------------+
; LPM_WIDTH ; 7 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_4nh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter:inst|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH ; 15 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_joh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/03-源码文件/VHDL/02-6位十进制计数器/Digital6Counter.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sat Mar 24 22:44:08 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Digital6Counter -c Digital6Counter
Info: Found 2 design units, including 1 entities, in source file counter.vhd
Info: Found design unit 1: counter-counter_architecture
Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file leddrv.vhd
Info: Found design unit 1: leddrv-leddrv_architecture
Info: Found entity 1: leddrv
Info: Found 1 design units, including 1 entities, in source file Digital6Counter.bdf
Info: Found entity 1: Digital6Counter
Info: Found 2 design units, including 1 entities, in source file choice1from6.vhd
Info: Found design unit 1: choice1from6-choice1from6_architecture
Info: Found entity 1: choice1from6
Info: Found 2 design units, including 1 entities, in source file seg7_leddrv.vhd
Info: Found design unit 1: seg7_leddrv-seg7_leddrv_architecture
Info: Found entity 1: seg7_leddrv
Info: Elaborating entity "Digital6Counter" for the top level hierarchy
Warning: Port "carrier" of type counter and instance "inst" is missing source signal
Warning: Port "counter" of type counter and instance "inst" is missing source signal
Warning: Port "carrier" of type counter and instance "inst1" is missing source signal
Warning: Port "counter" of type counter and instance "inst1" is missing source signal
Warning: Port "carrier" of type counter and instance "inst2" is missing source signal
Warning: Port "counter" of type counter and instance "inst2" is missing source signal
Warning: Port "carrier" of type counter and instance "inst3" is missing source signal
Warning: Port "counter" of type counter and instance "inst3" is missing source signal
Warning: Port "carrier" of type counter and instance "inst4" is missing source signal
Warning: Port "counter" of type counter and instance "inst4" is missing source signal
Warning: Port "carrier" of type counter and instance "inst5" is missing source signal
Warning: Port "counter" of type counter and instance "inst5" is missing source signal
Warning: Port "carrier" of type counter and instance "inst7" is missing source signal
Warning: Port "counter" of type counter and instance "inst7" is missing source signal
Warning: Port "carrier" of type counter and instance "inst6" is missing source signal
Warning: Port "counter" of type counter and instance "inst6" is missing source signal
Info: Elaborating entity "leddrv" for hierarchy "leddrv:inst10"
Info: Elaborating entity "counter" for hierarchy "counter:inst2"
Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "counter" for hierarchy "counter:inst1"
Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "counter" for hierarchy "counter:inst"
Warning (10492): VHDL Process Statement warning at counter.vhd(63): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "choice1from6" for hierarchy "choice1from6:inst8"
Info: Elaborating entity "seg7_leddrv" for hierarchy "seg7_leddrv:inst9"
Info (10425): VHDL Case Statement information at seg7_leddrv.vhd(69): OTHERS choice is never selected
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf
Info: Found entity 1: look_add
Info: Ignored 23 buffer(s)
Info: Ignored 23 SOFT buffer(s)
Info: Duplicate registers merged to single register
Info: Duplicate register "choice1from6:inst8|dp" merged to single register "choice1from6:inst8|led_cs[1]"
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Promoted clock signal driven by pin "clock" to global clock signal
Info: Implemented 135 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 22 output pins
Info: Implemented 111 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings
Info: Processing ended: Sat Mar 24 22:44:18 2007
Info: Elapsed time: 00:00:11
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