pwm_measure.tan.qmsg

VHDL基础的编程源代码

{ "Info" "ITDB_TH_RESULT" "pwm_m:inst2\|data\[7\] data_sel clock_24M -2.500 ns register " "Info: th for register \"pwm_m:inst2\|data\[7\]\" (data pin = \"data_sel\", clock pin = \"clock_24M\") is -2.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 105 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 105; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { clock_24M } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -120 80 248 -104 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_m:inst2\|data\[7\] 2 REG LC113 1 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC113; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "0.900 ns" { clock_24M pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns data_sel 1 PIN PIN_79 32 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_79; Fanout = 32; PIN Node = 'data_sel'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { data_sel } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -152 80 248 -136 "data_sel" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 7.200 ns pwm_m:inst2\|data\[7\] 2 REG LC113 1 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 7.200 ns; Loc. = LC113; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "5.800 ns" { data_sel pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 62.50 % ) " "Info: Total cell delay = 4.500 ns ( 62.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 37.50 % ) " "Info: Total interconnect delay = 2.700 ns ( 37.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "7.200 ns" { data_sel pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { data_sel data_sel~out pwm_m:inst2|data[7] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "7.200 ns" { data_sel pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { data_sel data_sel~out pwm_m:inst2|data[7] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 08 04:13:24 2007 " "Info: Processing ended: Sun Apr 08 04:13:24 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}