pwm_measure.tan.qmsg

VHDL基础的编程源代码

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock_24M " "Info: Assuming node \"clock_24M\" is an undefined clock" {  } { { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -120 80 248 -104 "clock_24M" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock_24M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register pwm_m:inst2\|lpm_counter:TL_counter_rtl_0\|dffs\[0\] register pwm_m:inst2\|data\[0\] 56.82 MHz 17.6 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 56.82 MHz between source register \"pwm_m:inst2\|lpm_counter:TL_counter_rtl_0\|dffs\[0\]\" and destination register \"pwm_m:inst2\|data\[0\]\" (period= 17.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.100 ns + Longest register register " "Info: + Longest register to register delay is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm_m:inst2\|lpm_counter:TL_counter_rtl_0\|dffs\[0\] 1 REG LC90 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC90; Fanout = 35; REG Node = 'pwm_m:inst2\|lpm_counter:TL_counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(4.400 ns) 7.300 ns pwm_m:inst2\|TL_value~125 2 COMB LC29 16 " "Info: 2: + IC(2.900 ns) + CELL(4.400 ns) = 7.300 ns; Loc. = LC29; Fanout = 16; COMB Node = 'pwm_m:inst2\|TL_value~125'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "7.300 ns" { pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] pwm_m:inst2|TL_value~125 } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 13.100 ns pwm_m:inst2\|data\[0\] 3 REG LC99 1 " "Info: 3: + IC(2.700 ns) + CELL(3.100 ns) = 13.100 ns; Loc. = LC99; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "5.800 ns" { pwm_m:inst2|TL_value~125 pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 57.25 % ) " "Info: Total cell delay = 7.500 ns ( 57.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns ( 42.75 % ) " "Info: Total interconnect delay = 5.600 ns ( 42.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "13.100 ns" { pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] pwm_m:inst2|TL_value~125 pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "13.100 ns" { pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] pwm_m:inst2|TL_value~125 pwm_m:inst2|data[0] } { 0.000ns 2.900ns 2.700ns } { 0.000ns 4.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 105 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 105; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { clock_24M } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -120 80 248 -104 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_m:inst2\|data\[0\] 2 REG LC99 1 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC99; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "0.900 ns" { clock_24M pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 105 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 105; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { clock_24M } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -120 80 248 -104 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_m:inst2\|lpm_counter:TL_counter_rtl_0\|dffs\[0\] 2 REG LC90 35 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC90; Fanout = 35; REG Node = 'pwm_m:inst2\|lpm_counter:TL_counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "0.900 ns" { clock_24M pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "13.100 ns" { pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] pwm_m:inst2|TL_value~125 pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "13.100 ns" { pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] pwm_m:inst2|TL_value~125 pwm_m:inst2|data[0] } { 0.000ns 2.900ns 2.700ns } { 0.000ns 4.400ns 3.100ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|lpm_counter:TL_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pwm_m:inst2\|data\[7\] pwm_in clock_24M 14.100 ns register " "Info: tsu for register \"pwm_m:inst2\|data\[7\]\" (data pin = \"pwm_in\", clock pin = \"clock_24M\") is 14.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.600 ns + Longest pin register " "Info: + Longest pin to register delay is 14.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns pwm_in 1 PIN PIN_77 128 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_77; Fanout = 128; PIN Node = 'pwm_in'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { pwm_in } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -136 80 248 -120 "pwm_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(4.400 ns) 8.800 ns pwm_m:inst2\|TH_value~121 2 COMB LC41 16 " "Info: 2: + IC(3.000 ns) + CELL(4.400 ns) = 8.800 ns; Loc. = LC41; Fanout = 16; COMB Node = 'pwm_m:inst2\|TH_value~121'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "7.400 ns" { pwm_in pwm_m:inst2|TH_value~121 } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 14.600 ns pwm_m:inst2\|data\[7\] 3 REG LC113 1 " "Info: 3: + IC(2.700 ns) + CELL(3.100 ns) = 14.600 ns; Loc. = LC113; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "5.800 ns" { pwm_m:inst2|TH_value~121 pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.900 ns ( 60.96 % ) " "Info: Total cell delay = 8.900 ns ( 60.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns ( 39.04 % ) " "Info: Total interconnect delay = 5.700 ns ( 39.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "14.600 ns" { pwm_in pwm_m:inst2|TH_value~121 pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "14.600 ns" { pwm_in pwm_in~out pwm_m:inst2|TH_value~121 pwm_m:inst2|data[7] } { 0.000ns 0.000ns 3.000ns 2.700ns } { 0.000ns 1.400ns 4.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 105 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 105; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { clock_24M } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -120 80 248 -104 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_m:inst2\|data\[7\] 2 REG LC113 1 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC113; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "0.900 ns" { clock_24M pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "14.600 ns" { pwm_in pwm_m:inst2|TH_value~121 pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "14.600 ns" { pwm_in pwm_in~out pwm_m:inst2|TH_value~121 pwm_m:inst2|data[7] } { 0.000ns 0.000ns 3.000ns 2.700ns } { 0.000ns 1.400ns 4.400ns 3.100ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M led_bits\[0\] pwm_m:inst2\|data\[0\] 6.600 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"led_bits\[0\]\" through register \"pwm_m:inst2\|data\[0\]\" is 6.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 105 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 105; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { clock_24M } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -120 80 248 -104 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_m:inst2\|data\[0\] 2 REG LC99 1 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC99; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "0.900 ns" { clock_24M pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm_m:inst2\|data\[0\] 1 REG LC99 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC99; Fanout = 1; REG Node = 'pwm_m:inst2\|data\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "" { pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "pwm_m.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_m.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns led_bits\[0\] 2 PIN PIN_64 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'led_bits\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "1.600 ns" { pwm_m:inst2|data[0] led_bits[0] } "NODE_NAME" } "" } } { "pwm_measure.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/pwm_measure.bdf" { { -152 424 600 -136 "led_bits\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "1.600 ns" { pwm_m:inst2|data[0] led_bits[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { pwm_m:inst2|data[0] led_bits[0] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "3.400 ns" { clock_24M pwm_m:inst2|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out pwm_m:inst2|data[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pwm_measure" "UNKNOWN" "V1" "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/db/pwm_measure.quartus_db" { Floorplan "U:/02-开发板/CA328/03-源码文件/VHDL/14-PWM信号测量/" "" "1.600 ns" { pwm_m:inst2|data[0] led_bits[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { pwm_m:inst2|data[0] led_bits[0] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}