buzzer.tan.qmsg

VHDL基础的编程源代码

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock_24M " "Info: Assuming node \"clock_24M\" is an undefined clock" {  } { { "buzzer.bdf" "" { Schematic "H:/03-源码文件/VHDL/09-蜂鸣器/buzzer.bdf" { { 120 256 424 136 "clock_24M" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock_24M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[0\] register counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[12\] 54.95 MHz 18.2 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 54.95 MHz between source register \"counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[0\]\" and destination register \"counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[12\]\" (period= 18.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.700 ns + Longest register register " "Info: + Longest register to register delay is 13.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[0\] 1 REG LC39 47 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 47; REG Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.400 ns) 7.600 ns counter:inst\|Equal~33 2 COMB LC30 14 " "Info: 2: + IC(3.200 ns) + CELL(4.400 ns) = 7.600 ns; Loc. = LC30; Fanout = 14; COMB Node = 'counter:inst\|Equal~33'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "7.600 ns" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] counter:inst|Equal~33 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.100 ns) 13.700 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[12\] 3 REG LC109 23 " "Info: 3: + IC(3.000 ns) + CELL(3.100 ns) = 13.700 ns; Loc. = LC109; Fanout = 23; REG Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[12\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "6.100 ns" { counter:inst|Equal~33 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 54.74 % ) " "Info: Total cell delay = 7.500 ns ( 54.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.200 ns ( 45.26 % ) " "Info: Total interconnect delay = 6.200 ns ( 45.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "13.700 ns" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] counter:inst|Equal~33 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "13.700 ns" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] counter:inst|Equal~33 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } { 0.000ns 3.200ns 3.000ns } { 0.000ns 4.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 17 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 17; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "" { clock_24M } "NODE_NAME" } "" } } { "buzzer.bdf" "" { Schematic "H:/03-源码文件/VHDL/09-蜂鸣器/buzzer.bdf" { { 120 256 424 136 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[12\] 2 REG LC109 23 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC109; Fanout = 23; REG Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[12\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "0.900 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 17 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 17; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "" { clock_24M } "NODE_NAME" } "" } } { "buzzer.bdf" "" { Schematic "H:/03-源码文件/VHDL/09-蜂鸣器/buzzer.bdf" { { 120 256 424 136 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[0\] 2 REG LC39 47 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC39; Fanout = 47; REG Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "0.900 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "13.700 ns" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] counter:inst|Equal~33 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "13.700 ns" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] counter:inst|Equal~33 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } { 0.000ns 3.200ns 3.000ns } { 0.000ns 4.400ns 3.100ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\] f_code\[3\] clock_24M 15.700 ns register " "Info: tsu for register \"counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\]\" (data pin = \"f_code\[3\]\", clock pin = \"clock_24M\") is 15.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.200 ns + Longest pin register " "Info: + Longest pin to register delay is 16.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns f_code\[3\] 1 PIN PIN_80 86 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_80; Fanout = 86; PIN Node = 'f_code\[3\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "" { f_code[3] } "NODE_NAME" } "" } } { "buzzer.bdf" "" { Schematic "H:/03-源码文件/VHDL/09-蜂鸣器/buzzer.bdf" { { 104 256 424 120 "f_code\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(4.400 ns) 8.700 ns counter:inst\|lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~24 2 COMB LC40 1 " "Info: 2: + IC(2.900 ns) + CELL(4.400 ns) = 8.700 ns; Loc. = LC40; Fanout = 1; COMB Node = 'counter:inst\|lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~24'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "7.300 ns" { f_code[3] counter:inst|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~24 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.300 ns) 12.600 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\]~210 3 COMB LC17 1 " "Info: 3: + IC(2.600 ns) + CELL(1.300 ns) = 12.600 ns; Loc. = LC17; Fanout = 1; COMB Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\]~210'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.900 ns" { counter:inst|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~24 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~210 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 13.500 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\]~216 4 COMB LC18 1 " "Info: 4: + IC(0.000 ns) + CELL(0.900 ns) = 13.500 ns; Loc. = LC18; Fanout = 1; COMB Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\]~216'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "0.900 ns" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~210 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~216 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 16.200 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\] 5 REG LC19 33 " "Info: 5: + IC(0.000 ns) + CELL(2.700 ns) = 16.200 ns; Loc. = LC19; Fanout = 33; REG Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "2.700 ns" { counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~216 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.700 ns ( 66.05 % ) " "Info: Total cell delay = 10.700 ns ( 66.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns ( 33.95 % ) " "Info: Total interconnect delay = 5.500 ns ( 33.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "16.200 ns" { f_code[3] counter:inst|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~24 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~210 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~216 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.200 ns" { f_code[3] f_code[3]~out counter:inst|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~24 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~210 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~216 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } { 0.000ns 0.000ns 2.900ns 2.600ns 0.000ns 0.000ns } { 0.000ns 1.400ns 4.400ns 1.300ns 0.900ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 17 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 17; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "" { clock_24M } "NODE_NAME" } "" } } { "buzzer.bdf" "" { Schematic "H:/03-源码文件/VHDL/09-蜂鸣器/buzzer.bdf" { { 120 256 424 136 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\] 2 REG LC19 33 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC19; Fanout = 33; REG Node = 'counter:inst\|lpm_counter:delay_counter_rtl_0\|dffs\[14\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "0.900 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "16.200 ns" { f_code[3] counter:inst|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~24 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~210 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~216 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "16.200 ns" { f_code[3] f_code[3]~out counter:inst|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~24 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~210 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14]~216 counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } { 0.000ns 0.000ns 2.900ns 2.600ns 0.000ns 0.000ns } { 0.000ns 1.400ns 4.400ns 1.300ns 0.900ns 2.700ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|lpm_counter:delay_counter_rtl_0|dffs[14] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M s_out counter:inst\|s_out 6.600 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"s_out\" through register \"counter:inst\|s_out\" is 6.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 17 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 17; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "" { clock_24M } "NODE_NAME" } "" } } { "buzzer.bdf" "" { Schematic "H:/03-源码文件/VHDL/09-蜂鸣器/buzzer.bdf" { { 120 256 424 136 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter:inst\|s_out 2 REG LC16 2 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC16; Fanout = 2; REG Node = 'counter:inst\|s_out'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "0.900 ns" { clock_24M counter:inst|s_out } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/09-蜂鸣器/counter.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|s_out } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|s_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/09-蜂鸣器/counter.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst\|s_out 1 REG LC16 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 2; REG Node = 'counter:inst\|s_out'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "" { counter:inst|s_out } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/09-蜂鸣器/counter.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns s_out 2 PIN PIN_92 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 's_out'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "1.600 ns" { counter:inst|s_out s_out } "NODE_NAME" } "" } } { "buzzer.bdf" "" { Schematic "H:/03-源码文件/VHDL/09-蜂鸣器/buzzer.bdf" { { 104 568 744 120 "s_out" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "1.600 ns" { counter:inst|s_out s_out } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { counter:inst|s_out s_out } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "3.400 ns" { clock_24M counter:inst|s_out } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M clock_24M~out counter:inst|s_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "buzzer" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/09-蜂鸣器/db/buzzer.quartus_db" { Floorplan "H:/03-源码文件/VHDL/09-蜂鸣器/" "" "1.600 ns" { counter:inst|s_out s_out } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { counter:inst|s_out s_out } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}