buzzer.hier_info

VHDL基础的编程源代码

|buzzer
s_out <= counter:inst.s_out
clock_24M => counter:inst.clock
reset => counter:inst.reset
f_code[0] => counter:inst.f_code[0]
f_code[1] => counter:inst.f_code[1]
f_code[2] => counter:inst.f_code[2]
f_code[3] => counter:inst.f_code[3]


|buzzer|counter:inst
s_out <= s_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
f_code[0] => Mux~0.IN19
f_code[0] => Mux~1.IN19
f_code[0] => Mux~2.IN19
f_code[0] => Mux~3.IN19
f_code[0] => Mux~4.IN19
f_code[0] => Mux~5.IN19
f_code[0] => Mux~6.IN19
f_code[0] => Mux~7.IN19
f_code[0] => Mux~8.IN19
f_code[0] => Mux~9.IN19
f_code[0] => Mux~10.IN19
f_code[0] => Mux~11.IN19
f_code[0] => Mux~12.IN10
f_code[0] => Mux~13.IN5
f_code[1] => Mux~0.IN18
f_code[1] => Mux~1.IN18
f_code[1] => Mux~2.IN18
f_code[1] => Mux~3.IN18
f_code[1] => Mux~4.IN18
f_code[1] => Mux~5.IN18
f_code[1] => Mux~6.IN18
f_code[1] => Mux~7.IN18
f_code[1] => Mux~8.IN18
f_code[1] => Mux~9.IN18
f_code[1] => Mux~10.IN18
f_code[1] => Mux~11.IN18
f_code[1] => Mux~12.IN9
f_code[1] => Mux~13.IN4
f_code[2] => Mux~0.IN17
f_code[2] => Mux~1.IN17
f_code[2] => Mux~2.IN17
f_code[2] => Mux~3.IN17
f_code[2] => Mux~4.IN17
f_code[2] => Mux~5.IN17
f_code[2] => Mux~6.IN17
f_code[2] => Mux~7.IN17
f_code[2] => Mux~8.IN17
f_code[2] => Mux~9.IN17
f_code[2] => Mux~10.IN17
f_code[2] => Mux~11.IN17
f_code[2] => Mux~12.IN8
f_code[3] => Mux~0.IN16
f_code[3] => Mux~1.IN16
f_code[3] => Mux~2.IN16
f_code[3] => Mux~3.IN16
f_code[3] => Mux~4.IN16
f_code[3] => Mux~5.IN16
f_code[3] => Mux~6.IN16
f_code[3] => Mux~7.IN16
f_code[3] => Mux~8.IN16
f_code[3] => Mux~9.IN16
f_code[3] => Mux~10.IN16
f_code[3] => Mux~11.IN16
clock => delay_counter[15].CLK
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => s_out~reg0.CLK
reset => process0~0.IN0