counter.vhd

VHDL基础的编程源代码

--/*****************************************************************************
-- * 源文件:	counter.vhd
-- * 模块:   	分频器
-- * 版权:
-- *         	Copyright(C) 北京联华众科科技有限公司
-- *						www.lianhua-zhongke.com.cn
-- * 版本：  	Version 1.0
-- * 
-- * 功能说明:
-- *		   	对输入时钟按照参数指定的分频系数进行分频输出
-- *
-- * 参数说明：
-- *	       	输出
-- *			s_out - 分频输出，它的频率由输入时钟和分频参数确定
-- *					  f_carrier = f_clock/f_code
-- *
-- *			输入
-- *			f_code - 分频系数设置值
-- *			clock - 时钟
-- *			reset - 复位信号，低电平有效
-- *
-- *			参数
-- *
-- * 变更记录: 
-- *         2006.01.28, 新建
-- *
-- *****************************************************************************/
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY counter IS
	PORT
	(
		s_out : BUFFER STD_LOGIC;
		
		f_code : IN STD_LOGIC_VECTOR(3 downto 0);--"0000":1kHz, "1111":约3.3kHz
		clock : IN STD_LOGIC;
		reset : IN STD_LOGIC
	);
	
END counter;


ARCHITECTURE counter_architecture OF counter IS	
BEGIN
	
	PROCESS(clock, reset)
		VARIABLE divisor : INTEGER RANGE 0 TO 65535;
		VARIABLE delay_counter : INTEGER RANGE 0 TO 65535;
	BEGIN		
		IF (reset = '0') THEN
			s_out <= '1';
			divisor := 0;
			delay_counter := 0;			
		ELSIF(clock = '1' AND clock'EVENT) THEN
			
			divisor := 7125;
			CASE f_code IS
				WHEN "0000" => divisor := 24000;--1kHz
				WHEN "0001" => divisor := 22875;
				WHEN "0010" => divisor := 21750;
				WHEN "0011" => divisor := 20625;
				WHEN "0100" => divisor := 19500;
				WHEN "0101" => divisor := 18375;
				WHEN "0110" => divisor := 17250;
				WHEN "0111" => divisor := 16125;
				WHEN "1000" => divisor := 15000;
				WHEN "1001" => divisor := 13875;
				WHEN "1010" => divisor := 12750;
				WHEN "1011" => divisor := 11625;
				WHEN "1100" => divisor := 10500;
				WHEN "1101" => divisor := 9375;
				WHEN "1110" => divisor := 8250;
				WHEN "1111" => divisor := 7125;--约3.3kHz
				WHEN OTHERS => divisor := 7125;
			END CASE;
			
			IF (delay_counter = divisor/2-1) THEN
				s_out <= NOT s_out;
				delay_counter := 0;			
			ELSE
				delay_counter := delay_counter+1;
			END IF;
		END IF;
		
	END PROCESS;

END counter_architecture;