reset_key.tan.qmsg

VHDL基础的编程源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 26 09:18:33 2007 " "Info: Processing started: Mon Mar 26 09:18:33 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off reset_key -c reset_key " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off reset_key -c reset_key" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key20_in key20_out 10.000 ns Longest " "Info: Longest tpd from source pin \"key20_in\" to destination pin \"key20_out\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns key20_in 1 PIN PIN_61 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_61; Fanout = 1; PIN Node = 'key20_in'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "reset_key" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/10-复位及独立按键/db/reset_key.quartus_db" { Floorplan "H:/03-源码文件/VHDL/10-复位及独立按键/" "" "" { key20_in } "NODE_NAME" } "" } } { "reset_key.bdf" "" { Schematic "H:/03-源码文件/VHDL/10-复位及独立按键/reset_key.bdf" { { 240 240 408 256 "key20_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.400 ns) 8.400 ns key20_in~2 2 COMB LC105 1 " "Info: 2: + IC(2.600 ns) + CELL(4.400 ns) = 8.400 ns; Loc. = LC105; Fanout = 1; COMB Node = 'key20_in~2'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "reset_key" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/10-复位及独立按键/db/reset_key.quartus_db" { Floorplan "H:/03-源码文件/VHDL/10-复位及独立按键/" "" "7.000 ns" { key20_in key20_in~2 } "NODE_NAME" } "" } } { "reset_key.bdf" "" { Schematic "H:/03-源码文件/VHDL/10-复位及独立按键/reset_key.bdf" { { 240 240 408 256 "key20_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.000 ns key20_out 3 PIN PIN_69 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'key20_out'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "reset_key" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/10-复位及独立按键/db/reset_key.quartus_db" { Floorplan "H:/03-源码文件/VHDL/10-复位及独立按键/" "" "1.600 ns" { key20_in~2 key20_out } "NODE_NAME" } "" } } { "reset_key.bdf" "" { Schematic "H:/03-源码文件/VHDL/10-复位及独立按键/reset_key.bdf" { { 240 504 680 256 "key20_out" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 74.00 % ) " "Info: Total cell delay = 7.400 ns ( 74.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 26.00 % ) " "Info: Total interconnect delay = 2.600 ns ( 26.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "reset_key" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/10-复位及独立按键/db/reset_key.quartus_db" { Floorplan "H:/03-源码文件/VHDL/10-复位及独立按键/" "" "10.000 ns" { key20_in key20_in~2 key20_out } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { key20_in key20_in~out key20_in~2 key20_out } { 0.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 1.400ns 4.400ns 1.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 26 09:18:33 2007 " "Info: Processing ended: Mon Mar 26 09:18:33 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}