pwm_gen.hier_info

VHDL基础的编程源代码

|pwm_gen
tx <= serialport_tx:inst5.tx
clock_24M => pwm_counter:inst.clock
clock_24M => counter:inst3.clock
reset => pwm_counter:inst.reset
reset => counter:inst3.reset
reset => pwm:inst4.reset
reset => serialport_tx:inst5.reset
s_pwm <= pwm_counter:inst.pwm_out
Vref <= <VCC>


|pwm_gen|serialport_tx:inst5
tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_ready => comb~0.IN0
data_ready => idata~0.OUTPUTSELECT
data_ready => idata~1.OUTPUTSELECT
data_ready => idata~2.OUTPUTSELECT
data_ready => idata~3.OUTPUTSELECT
data_ready => idata~4.OUTPUTSELECT
data_ready => idata~5.OUTPUTSELECT
data_ready => idata~6.OUTPUTSELECT
data_ready => idata~7.OUTPUTSELECT
data_ready => nextState~7.DATAB
data[0] => idata~7.DATAB
data[1] => idata~6.DATAB
data[2] => idata~5.DATAB
data[3] => idata~4.DATAB
data[4] => idata~3.DATAB
data[5] => idata~2.DATAB
data[6] => idata~1.DATAB
data[7] => idata~0.DATAB
clock => nextState[3].CLK
clock => nextState[2].CLK
clock => nextState[1].CLK
clock => nextState[0].CLK
clock => bit_index[2].CLK
clock => bit_index[1].CLK
clock => bit_index[0].CLK
clock => idata[7].CLK
clock => idata[6].CLK
clock => idata[5].CLK
clock => idata[4].CLK
clock => idata[3].CLK
clock => idata[2].CLK
clock => idata[1].CLK
clock => idata[0].CLK
clock => tx~reg0.CLK
reset => process0~0.IN0


|pwm_gen|pwm:inst4
clock_out <= clock_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_m => clock_out~0.OUTPUTSELECT
clock_m => delay_counter~32.OUTPUTSELECT
clock_m => delay_counter~33.OUTPUTSELECT
clock_m => delay_counter~34.OUTPUTSELECT
clock_m => delay_counter~35.OUTPUTSELECT
clock_m => delay_counter~36.OUTPUTSELECT
clock_m => delay_counter~37.OUTPUTSELECT
clock_m => delay_counter~38.OUTPUTSELECT
clock_m => delay_counter~39.OUTPUTSELECT
clock_m => delay_counter~40.OUTPUTSELECT
clock_m => delay_counter~41.OUTPUTSELECT
clock_m => delay_counter~42.OUTPUTSELECT
clock_m => delay_counter~43.OUTPUTSELECT
clock_m => delay_counter~44.OUTPUTSELECT
clock_m => delay_counter~45.OUTPUTSELECT
clock_m => delay_counter~46.OUTPUTSELECT
clock_m => delay_counter~47.OUTPUTSELECT
clock_m => delay_counter~48.OUTPUTSELECT
clock_m => delay_counter~49.OUTPUTSELECT
clock_m => delay_counter~50.OUTPUTSELECT
clock_m => delay_counter~51.OUTPUTSELECT
clock_m => delay_counter~52.OUTPUTSELECT
clock_m => delay_counter~53.OUTPUTSELECT
clock_m => delay_counter~54.OUTPUTSELECT
clock_m => delay_counter~55.OUTPUTSELECT
clock_m => delay_counter~56.OUTPUTSELECT
clock_m => delay_counter~57.OUTPUTSELECT
clock_m => delay_counter~58.OUTPUTSELECT
clock_m => delay_counter~59.OUTPUTSELECT
clock_m => delay_counter~60.OUTPUTSELECT
clock_m => delay_counter~61.OUTPUTSELECT
clock_m => delay_counter~62.OUTPUTSELECT
clock_m => delay_counter~63.OUTPUTSELECT
clock => delay_counter[31].CLK
clock => delay_counter[30].CLK
clock => delay_counter[29].CLK
clock => delay_counter[28].CLK
clock => delay_counter[27].CLK
clock => delay_counter[26].CLK
clock => delay_counter[25].CLK
clock => delay_counter[24].CLK
clock => delay_counter[23].CLK
clock => delay_counter[22].CLK
clock => delay_counter[21].CLK
clock => delay_counter[20].CLK
clock => delay_counter[19].CLK
clock => delay_counter[18].CLK
clock => delay_counter[17].CLK
clock => delay_counter[16].CLK
clock => delay_counter[15].CLK
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => clock_out~reg0.CLK
reset => process0~0.IN0


|pwm_gen|pwm_counter:inst
data[0] <= data~13.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data~12.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data~11.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data~10.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data~9.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data~8.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data~7.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= <GND>
send_timer <= send_timer~reg0.DB_MAX_OUTPUT_PORT_TYPE
pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => send_counter[21].CLK
clock => send_counter[20].CLK
clock => send_counter[19].CLK
clock => send_counter[18].CLK
clock => send_counter[17].CLK
clock => send_counter[16].CLK
clock => send_counter[15].CLK
clock => send_counter[14].CLK
clock => send_counter[13].CLK
clock => send_counter[12].CLK
clock => send_counter[11].CLK
clock => send_counter[10].CLK
clock => send_counter[9].CLK
clock => send_counter[8].CLK
clock => send_counter[7].CLK
clock => send_counter[6].CLK
clock => send_counter[5].CLK
clock => send_counter[4].CLK
clock => send_counter[3].CLK
clock => send_counter[2].CLK
clock => send_counter[1].CLK
clock => send_counter[0].CLK
clock => byte_index[4].CLK
clock => byte_index[3].CLK
clock => byte_index[2].CLK
clock => byte_index[1].CLK
clock => byte_index[0].CLK
clock => send_timer~reg0.CLK
clock => pwm_out~reg0.CLK
reset => process1~0.IN0


|pwm_gen|counter:inst3
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE