pwm_gen.map.qmsg

VHDL基础的编程源代码

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "serialport_tx:inst5\|idata\[7\] data_in GND " "Warning: Reduced register \"serialport_tx:inst5\|idata\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "pwm:inst4\|delay_counter\[0\]~64 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"pwm:inst4\|delay_counter\[0\]~64\"" {  } { { "pwm.vhd" "delay_counter\[0\]~64" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm.vhd" 62 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "55 " "Info: Ignored 55 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "55 " "Info: Ignored 55 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "counter:inst3\|delay_counter\[0\] pwm_counter:inst\|delay_counter\[0\] " "Info: Duplicate register \"counter:inst3\|delay_counter\[0\]\" merged to single register \"pwm_counter:inst\|delay_counter\[0\]\"" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/counter.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pwm_counter:inst\|send_counter\[0\] pwm_counter:inst\|delay_counter\[0\] " "Info: Duplicate register \"pwm_counter:inst\|send_counter\[0\]\" merged to single register \"pwm_counter:inst\|delay_counter\[0\]\"" {  } { { "pwm_counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/serialport_tx.vhd" 41 -1 0 } } { "pwm_counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_counter.vhd" 60 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/counter.vhd" 50 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Vref VCC " "Warning: Pin \"Vref\" stuck at VCC" {  } { { "pwm_gen.bdf" "" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { { 216 784 960 232 "Vref" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock_24M " "Info: Promoted clock signal driven by pin \"clock_24M\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "124 " "Info: Implemented 124 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "116 " "Info: Implemented 116 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "3 " "Info: Implemented 3 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 26 11:14:44 2007 " "Info: Processing ended: Mon Mar 26 11:14:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}