pwm_gen.map.qmsg

VHDL基础的编程源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 26 11:14:33 2007 " "Info: Processing started: Mon Mar 26 11:14:33 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pwm_gen -c pwm_gen " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pwm_gen -c pwm_gen" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_architecture " "Info: Found design unit 1: counter-counter_architecture" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/counter.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/counter.vhd" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm-pwm_architecture " "Info: Found design unit 1: pwm-pwm_architecture" {  } { { "pwm.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Info: Found entity 1: pwm" {  } { { "pwm.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm.vhd" 34 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm_gen.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pwm_gen.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_gen " "Info: Found entity 1: pwm_gen" {  } { { "pwm_gen.bdf" "" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serialport_tx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serialport_tx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serialport_tx-serialport_tx_architecture " "Info: Found design unit 1: serialport_tx-serialport_tx_architecture" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/serialport_tx.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 serialport_tx " "Info: Found entity 1: serialport_tx" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/serialport_tx.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm_counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm_counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm_counter-pwm_architecture " "Info: Found design unit 1: pwm_counter-pwm_architecture" {  } { { "pwm_counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_counter.vhd" 69 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm_counter " "Info: Found entity 1: pwm_counter" {  } { { "pwm_counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_counter.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pwm_gen " "Info: Elaborating entity \"pwm_gen\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst3 " "Warning: Port \"carrier\" of type counter and instance \"inst3\" is missing source signal" {  } { { "pwm_gen.bdf" "" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { { 448 200 344 544 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst3 " "Warning: Port \"counter\" of type counter and instance \"inst3\" is missing source signal" {  } { { "pwm_gen.bdf" "" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { { 448 200 344 544 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serialport_tx serialport_tx:inst5 " "Info: Elaborating entity \"serialport_tx\" for hierarchy \"serialport_tx:inst5\"" {  } { { "pwm_gen.bdf" "inst5" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { { 280 664 784 408 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "tmp serialport_tx.vhd(62) " "Info (10035): Verilog HDL or VHDL information at serialport_tx.vhd(62): object \"tmp\" declared but not used" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/serialport_tx.vhd" 62 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:inst4 " "Info: Elaborating entity \"pwm\" for hierarchy \"pwm:inst4\"" {  } { { "pwm_gen.bdf" "inst4" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { { 280 408 552 376 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_counter pwm_counter:inst " "Info: Elaborating entity \"pwm_counter\" for hierarchy \"pwm_counter:inst\"" {  } { { "pwm_gen.bdf" "inst" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { { 128 200 336 224 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "pwm_counter.vhd(118) " "Info (10425): VHDL Case Statement information at pwm_counter.vhd(118): OTHERS choice is never selected" {  } { { "pwm_counter.vhd" "" { Text "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_counter.vhd" 118 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst3 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst3\"" {  } { { "pwm_gen.bdf" "inst3" { Schematic "H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.bdf" { { 448 200 344 544 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}