crystal.tan.qmsg

VHDL基础的编程源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_40M register counter:inst1\|delay_counter\[0\] register counter:inst1\|delay_counter\[8\] 82.64 MHz 12.1 ns Internal " "Info: Clock \"clock_40M\" has Internal fmax of 82.64 MHz between source register \"counter:inst1\|delay_counter\[0\]\" and destination register \"counter:inst1\|delay_counter\[8\]\" (period= 12.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register register " "Info: + Longest register to register delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst1\|delay_counter\[0\] 1 REG LC3 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 36; REG Node = 'counter:inst1\|delay_counter\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { counter:inst1|delay_counter[0] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 4.000 ns counter:inst1\|delay_counter~144 2 COMB LC97 1 " "Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 4.000 ns; Loc. = LC97; Fanout = 1; COMB Node = 'counter:inst1\|delay_counter~144'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "4.000 ns" { counter:inst1|delay_counter[0] counter:inst1|delay_counter~144 } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.900 ns counter:inst1\|delay_counter~146 3 COMB LC98 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.900 ns; Loc. = LC98; Fanout = 1; COMB Node = 'counter:inst1\|delay_counter~146'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "0.900 ns" { counter:inst1|delay_counter~144 counter:inst1|delay_counter~146 } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 7.600 ns counter:inst1\|delay_counter\[8\] 4 REG LC99 34 " "Info: 4: + IC(0.000 ns) + CELL(2.700 ns) = 7.600 ns; Loc. = LC99; Fanout = 34; REG Node = 'counter:inst1\|delay_counter\[8\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "2.700 ns" { counter:inst1|delay_counter~146 counter:inst1|delay_counter[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns ( 64.47 % ) " "Info: Total cell delay = 4.900 ns ( 64.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 35.53 % ) " "Info: Total interconnect delay = 2.700 ns ( 35.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "7.600 ns" { counter:inst1|delay_counter[0] counter:inst1|delay_counter~144 counter:inst1|delay_counter~146 counter:inst1|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { counter:inst1|delay_counter[0] counter:inst1|delay_counter~144 counter:inst1|delay_counter~146 counter:inst1|delay_counter[8] } { 0.000ns 2.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_40M destination 6.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_40M\" to destination register is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns clock_40M 1 CLK PIN_54 27 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_54; Fanout = 27; CLK Node = 'clock_40M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { clock_40M } "NODE_NAME" } "" } } { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 280 120 288 296 "clock_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 6.300 ns counter:inst1\|delay_counter\[8\] 2 REG LC99 34 " "Info: 2: + IC(2.700 ns) + CELL(2.200 ns) = 6.300 ns; Loc. = LC99; Fanout = 34; REG Node = 'counter:inst1\|delay_counter\[8\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "4.900 ns" { clock_40M counter:inst1|delay_counter[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 57.14 % ) " "Info: Total cell delay = 3.600 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 42.86 % ) " "Info: Total interconnect delay = 2.700 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.300 ns" { clock_40M counter:inst1|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.300 ns" { clock_40M clock_40M~out counter:inst1|delay_counter[8] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_40M source 6.300 ns - Longest register " "Info: - Longest clock path from clock \"clock_40M\" to source register is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns clock_40M 1 CLK PIN_54 27 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_54; Fanout = 27; CLK Node = 'clock_40M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { clock_40M } "NODE_NAME" } "" } } { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 280 120 288 296 "clock_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 6.300 ns counter:inst1\|delay_counter\[0\] 2 REG LC3 36 " "Info: 2: + IC(2.700 ns) + CELL(2.200 ns) = 6.300 ns; Loc. = LC3; Fanout = 36; REG Node = 'counter:inst1\|delay_counter\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "4.900 ns" { clock_40M counter:inst1|delay_counter[0] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 57.14 % ) " "Info: Total cell delay = 3.600 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 42.86 % ) " "Info: Total interconnect delay = 2.700 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.300 ns" { clock_40M counter:inst1|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.300 ns" { clock_40M clock_40M~out counter:inst1|delay_counter[0] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.300 ns" { clock_40M counter:inst1|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.300 ns" { clock_40M clock_40M~out counter:inst1|delay_counter[8] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.300 ns" { clock_40M counter:inst1|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.300 ns" { clock_40M clock_40M~out counter:inst1|delay_counter[0] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "7.600 ns" { counter:inst1|delay_counter[0] counter:inst1|delay_counter~144 counter:inst1|delay_counter~146 counter:inst1|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { counter:inst1|delay_counter[0] counter:inst1|delay_counter~144 counter:inst1|delay_counter~146 counter:inst1|delay_counter[8] } { 0.000ns 2.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.300 ns" { clock_40M counter:inst1|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.300 ns" { clock_40M clock_40M~out counter:inst1|delay_counter[8] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.300 ns" { clock_40M counter:inst1|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.300 ns" { clock_40M clock_40M~out counter:inst1|delay_counter[0] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M clock_1s_1 counter:inst\|carrier 9.600 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"clock_1s_1\" through register \"counter:inst\|carrier\" is 9.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 6.400 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns clock_24M 1 CLK PIN_52 26 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_52; Fanout = 26; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { clock_24M } "NODE_NAME" } "" } } { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 112 120 288 128 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 6.400 ns counter:inst\|carrier 2 REG LC113 2 " "Info: 2: + IC(2.800 ns) + CELL(2.200 ns) = 6.400 ns; Loc. = LC113; Fanout = 2; REG Node = 'counter:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "5.000 ns" { clock_24M counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 56.25 % ) " "Info: Total cell delay = 3.600 ns ( 56.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 43.75 % ) " "Info: Total interconnect delay = 2.800 ns ( 43.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|carrier } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|carrier } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst\|carrier 1 REG LC113 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC113; Fanout = 2; REG Node = 'counter:inst\|carrier'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clock_1s_1 2 PIN PIN_75 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'clock_1s_1'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "1.600 ns" { counter:inst|carrier clock_1s_1 } "NODE_NAME" } "" } } { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 128 464 640 144 "clock_1s_1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "1.600 ns" { counter:inst|carrier clock_1s_1 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { counter:inst|carrier clock_1s_1 } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|carrier } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|carrier } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "1.600 ns" { counter:inst|carrier clock_1s_1 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { counter:inst|carrier clock_1s_1 } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 26 09:48:49 2007 " "Info: Processing ended: Mon Mar 26 09:48:49 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}