crystal.tan.qmsg

VHDL基础的编程源代码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock_24M " "Info: Assuming node \"clock_24M\" is an undefined clock" {  } { { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 112 120 288 128 "clock_24M" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock_24M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clock_40M " "Info: Assuming node \"clock_40M\" is an undefined clock" {  } { { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 280 120 288 296 "clock_40M" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock_40M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register counter:inst\|delay_counter\[0\] register counter:inst\|delay_counter\[8\] 81.97 MHz 12.2 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 81.97 MHz between source register \"counter:inst\|delay_counter\[0\]\" and destination register \"counter:inst\|delay_counter\[8\]\" (period= 12.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Longest register register " "Info: + Longest register to register delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst\|delay_counter\[0\] 1 REG LC1 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 37; REG Node = 'counter:inst\|delay_counter\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.300 ns) 4.100 ns counter:inst\|delay_counter~171 2 COMB LC116 1 " "Info: 2: + IC(2.800 ns) + CELL(1.300 ns) = 4.100 ns; Loc. = LC116; Fanout = 1; COMB Node = 'counter:inst\|delay_counter~171'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "4.100 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~171 } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 5.000 ns counter:inst\|delay_counter~173 3 COMB LC117 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 5.000 ns; Loc. = LC117; Fanout = 1; COMB Node = 'counter:inst\|delay_counter~173'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "0.900 ns" { counter:inst|delay_counter~171 counter:inst|delay_counter~173 } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 7.700 ns counter:inst\|delay_counter\[8\] 4 REG LC118 34 " "Info: 4: + IC(0.000 ns) + CELL(2.700 ns) = 7.700 ns; Loc. = LC118; Fanout = 34; REG Node = 'counter:inst\|delay_counter\[8\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "2.700 ns" { counter:inst|delay_counter~173 counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns ( 63.64 % ) " "Info: Total cell delay = 4.900 ns ( 63.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 36.36 % ) " "Info: Total interconnect delay = 2.800 ns ( 36.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "7.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~171 counter:inst|delay_counter~173 counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~171 counter:inst|delay_counter~173 counter:inst|delay_counter[8] } { 0.000ns 2.800ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 6.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns clock_24M 1 CLK PIN_52 26 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_52; Fanout = 26; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { clock_24M } "NODE_NAME" } "" } } { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 112 120 288 128 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 6.400 ns counter:inst\|delay_counter\[8\] 2 REG LC118 34 " "Info: 2: + IC(2.800 ns) + CELL(2.200 ns) = 6.400 ns; Loc. = LC118; Fanout = 34; REG Node = 'counter:inst\|delay_counter\[8\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "5.000 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 56.25 % ) " "Info: Total cell delay = 3.600 ns ( 56.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 43.75 % ) " "Info: Total interconnect delay = 2.800 ns ( 43.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[8] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 6.400 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns clock_24M 1 CLK PIN_52 26 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_52; Fanout = 26; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "" { clock_24M } "NODE_NAME" } "" } } { "crystal.bdf" "" { Schematic "H:/03-源码文件/VHDL/12-晶振测试/crystal.bdf" { { 112 120 288 128 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 6.400 ns counter:inst\|delay_counter\[0\] 2 REG LC1 37 " "Info: 2: + IC(2.800 ns) + CELL(2.200 ns) = 6.400 ns; Loc. = LC1; Fanout = 37; REG Node = 'counter:inst\|delay_counter\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "5.000 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 56.25 % ) " "Info: Total cell delay = 3.600 ns ( 56.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 43.75 % ) " "Info: Total interconnect delay = 2.800 ns ( 43.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[0] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[8] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[0] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/12-晶振测试/counter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "7.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~171 counter:inst|delay_counter~173 counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.700 ns" { counter:inst|delay_counter[0] counter:inst|delay_counter~171 counter:inst|delay_counter~173 counter:inst|delay_counter[8] } { 0.000ns 2.800ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|delay_counter[8] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[8] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crystal" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/12-晶振测试/db/crystal.quartus_db" { Floorplan "H:/03-源码文件/VHDL/12-晶振测试/" "" "6.400 ns" { clock_24M counter:inst|delay_counter[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.400 ns" { clock_24M clock_24M~out counter:inst|delay_counter[0] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 2.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}