crystal.hier_info

VHDL基础的编程源代码

|crystal
clock_1s_1 <= counter:inst.carrier
clock_24M => counter:inst.clock
reset => counter:inst.reset
reset => counter:inst1.reset
clock_1s_2 <= counter:inst1.carrier
clock_40M => counter:inst1.clock


|crystal|counter:inst
clock => delay_counter[24].CLK
clock => delay_counter[23].CLK
clock => delay_counter[22].CLK
clock => delay_counter[21].CLK
clock => delay_counter[20].CLK
clock => delay_counter[19].CLK
clock => delay_counter[18].CLK
clock => delay_counter[17].CLK
clock => delay_counter[16].CLK
clock => delay_counter[15].CLK
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE


|crystal|counter:inst1
clock => delay_counter[25].CLK
clock => delay_counter[24].CLK
clock => delay_counter[23].CLK
clock => delay_counter[22].CLK
clock => delay_counter[21].CLK
clock => delay_counter[20].CLK
clock => delay_counter[19].CLK
clock => delay_counter[18].CLK
clock => delay_counter[17].CLK
clock => delay_counter[16].CLK
clock => delay_counter[15].CLK
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE