blockram.v

xilinx BlockRAM 级联

      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA13),       // Port A RAM Enable Input
      .ENB(ENB13),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM14 (
      .DOA(DOA14),       // Port A 16-bit Data Output
      .DOB(DOB14),       // Port B 32-bit Data Output
      .DOPA(DOPA14),     // Port A 2-bit Parity Output
      .DOPB(DOPB14),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA14),       // Port A RAM Enable Input
      .ENB(ENB14),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM15 (
      .DOA(DOA15),       // Port A 16-bit Data Output
      .DOB(DOB15),       // Port B 32-bit Data Output
      .DOPA(DOPA15),     // Port A 2-bit Parity Output
      .DOPB(DOPB15),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA15),       // Port A RAM Enable Input
      .ENB(ENB15),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM16 (
      .DOA(DOA16),       // Port A 16-bit Data Output
      .DOB(DOB16),       // Port B 32-bit Data Output
      .DOPA(DOPA16),     // Port A 2-bit Parity Output
      .DOPB(DOPB16),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA16),       // Port A RAM Enable Input
      .ENB(ENB16),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM17 (
      .DOA(DOA17),       // Port A 16-bit Data Output
      .DOB(DOB17),       // Port B 32-bit Data Output
      .DOPA(DOPA17),     // Port A 2-bit Parity Output
      .DOPB(DOPB17),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA17),       // Port A RAM Enable Input
      .ENB(ENB17),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM18 (
      .DOA(DOA18),       // Port A 16-bit Data Output
      .DOB(DOB18),       // Port B 32-bit Data Output
      .DOPA(DOPA18),     // Port A 2-bit Parity Output
      .DOPB(DOPB18),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA18),       // Port A RAM Enable Input
      .ENB(ENB18),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM19 (
      .DOA(DOA19),       // Port A 16-bit Data Output
      .DOB(DOB19),       // Port B 32-bit Data Output
      .DOPA(DOPA19),     // Port A 2-bit Parity Output
      .DOPB(DOPB19),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA19),       // Port A RAM Enable Input
      .ENB(ENB19),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM20 (
      .DOA(DOA20),       // Port A 16-bit Data Output
      .DOB(DOB20),       // Port B 32-bit Data Output
      .DOPA(DOPA20),     // Port A 2-bit Parity Output
      .DOPB(DOPB20),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA20),       // Port A RAM Enable Input
      .ENB(ENB20),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM21 (
      .DOA(DOA21),       // Port A 16-bit Data Output
      .DOB(DOB21),       // Port B 32-bit Data Output
      .DOPA(DOPA21),     // Port A 2-bit Parity Output
      .DOPB(DOPB21),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA21),       // Port A RAM Enable Input
      .ENB(ENB21),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM22 (
      .DOA(DOA22),       // Port A 16-bit Data Output
      .DOB(DOB22),       // Port B 32-bit Data Output
      .DOPA(DOPA22),     // Port A 2-bit Parity Output
      .DOPB(DOPB22),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA22),       // Port A RAM Enable Input
      .ENB(ENB22),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM23 (
      .DOA(DOA23),       // Port A 16-bit Data Output
      .DOB(DOB23),       // Port B 32-bit Data Output
      .DOPA(DOPA23),     // Port A 2-bit Parity Output
      .DOPB(DOPB23),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA23),       // Port A RAM Enable Input
      .ENB(ENB23),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM24 (
      .DOA(DOA24),       // Port A 16-bit Data Output
      .DOB(DOB24),       // Port B 32-bit Data Output
      .DOPA(DOPA24),     // Port A 2-bit Parity Output
      .DOPB(DOPB24),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA24),       // Port A RAM Enable Input
      .ENB(ENB24),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM25 (
      .DOA(DOA25),       // Port A 16-bit Data Output
      .DOB(DOB25),       // Port B 32-bit Data Output
      .DOPA(DOPA25),     // Port A 2-bit Parity Output
      .DOPB(DOPB25),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA25),       // Port A RAM Enable Input
      .ENB(ENB25),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );
RAMB16_S18_S36 BRAM26 (
      .DOA(DOA26),       // Port A 16-bit Data Output
      .DOB(DOB26),       // Port B 32-bit Data Output
      .DOPA(DOPA26),     // Port A 2-bit Parity Output
      .DOPB(DOPB26),     // Port B 4-bit Parity Output
      .ADDRA(ADDRA[9:0]),   // Port A 10-bit Address Input
      .ADDRB(ADDRB[8:0]),   // Port B 9-bit Address Input
      .CLKA(CLKA),     // Port A Clock
      .CLKB(CLKB),     // Port B Clock
      .DIA(DIA),       // Port A 16-bit Data Input
      .DIB(DIB),       // Port B 32-bit Data Input
      .DIPA(DIPA),     // Port A 2-bit parity Input
      .DIPB(DIPB),     // Port-B 4-bit parity Input
      .ENA(ENA26),       // Port A RAM Enable Input
      .ENB(ENB26),       // PortB RAM Enable Input
      .SSRA(SSRA),     // Port A Synchronous Set/Reset Input
      .SSRB(SSRB),     // Port B Synchronous Set/Reset Input
      .WEA(WEA),       // Port A Write Enable Input
      .WEB(WEB)        // Port B Write Enable Input
   );

endmodule