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5'b10010: DOPB = DOPB18 ;
5'b10011: DOPB = DOPB19 ;
5'b10100: DOPB = DOPB20 ;
5'b10101: DOPB = DOPB21 ;
5'b10110: DOPB = DOPB22 ;
5'b10111: DOPB = DOPB23 ;
5'b11000: DOPB = DOPB24 ;
5'b11001: DOPB = DOPB25 ;
5'b11010: DOPB = DOPB26 ;
default: DOPB = 4'h0;
endcase
RAMB16_S18_S36 BRAM00 (
.DOA(DOA00), // Port A 16-bit Data Output
.DOB(DOB00), // Port B 32-bit Data Output
.DOPA(DOPA00), // Port A 2-bit Parity Output
.DOPB(DOPB00), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA00), // Port A RAM Enable Input
.ENB(ENB00), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM01 (
.DOA(DOA01), // Port A 16-bit Data Output
.DOB(DOB01), // Port B 32-bit Data Output
.DOPA(DOPA01), // Port A 2-bit Parity Output
.DOPB(DOPB01), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA01), // Port A RAM Enable Input
.ENB(ENB01), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM02 (
.DOA(DOA02), // Port A 16-bit Data Output
.DOB(DOB02), // Port B 32-bit Data Output
.DOPA(DOPA02), // Port A 2-bit Parity Output
.DOPB(DOPB02), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA02), // Port A RAM Enable Input
.ENB(ENB02), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM03 (
.DOA(DOA03), // Port A 16-bit Data Output
.DOB(DOB03), // Port B 32-bit Data Output
.DOPA(DOPA03), // Port A 2-bit Parity Output
.DOPB(DOPB03), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA03), // Port A RAM Enable Input
.ENB(ENB03), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM04 (
.DOA(DOA04), // Port A 16-bit Data Output
.DOB(DOB04), // Port B 32-bit Data Output
.DOPA(DOPA04), // Port A 2-bit Parity Output
.DOPB(DOPB04), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA04), // Port A RAM Enable Input
.ENB(ENB04), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM05 (
.DOA(DOA05), // Port A 16-bit Data Output
.DOB(DOB05), // Port B 32-bit Data Output
.DOPA(DOPA05), // Port A 2-bit Parity Output
.DOPB(DOPB05), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA05), // Port A RAM Enable Input
.ENB(ENB05), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM06 (
.DOA(DOA06), // Port A 16-bit Data Output
.DOB(DOB06), // Port B 32-bit Data Output
.DOPA(DOPA06), // Port A 2-bit Parity Output
.DOPB(DOPB06), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA06), // Port A RAM Enable Input
.ENB(ENB06), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM07 (
.DOA(DOA07), // Port A 16-bit Data Output
.DOB(DOB07), // Port B 32-bit Data Output
.DOPA(DOPA07), // Port A 2-bit Parity Output
.DOPB(DOPB07), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA07), // Port A RAM Enable Input
.ENB(ENB07), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM08 (
.DOA(DOA08), // Port A 16-bit Data Output
.DOB(DOB08), // Port B 32-bit Data Output
.DOPA(DOPA08), // Port A 2-bit Parity Output
.DOPB(DOPB08), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA08), // Port A RAM Enable Input
.ENB(ENB08), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM09 (
.DOA(DOA09), // Port A 16-bit Data Output
.DOB(DOB09), // Port B 32-bit Data Output
.DOPA(DOPA09), // Port A 2-bit Parity Output
.DOPB(DOPB09), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA09), // Port A RAM Enable Input
.ENB(ENB09), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM10 (
.DOA(DOA10), // Port A 16-bit Data Output
.DOB(DOB10), // Port B 32-bit Data Output
.DOPA(DOPA10), // Port A 2-bit Parity Output
.DOPB(DOPB10), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA10), // Port A RAM Enable Input
.ENB(ENB10), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM11 (
.DOA(DOA11), // Port A 16-bit Data Output
.DOB(DOB11), // Port B 32-bit Data Output
.DOPA(DOPA11), // Port A 2-bit Parity Output
.DOPB(DOPB11), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA11), // Port A RAM Enable Input
.ENB(ENB11), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM12 (
.DOA(DOA12), // Port A 16-bit Data Output
.DOB(DOB12), // Port B 32-bit Data Output
.DOPA(DOPA12), // Port A 2-bit Parity Output
.DOPB(DOPB12), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
.ADDRB(ADDRB[8:0]), // Port B 9-bit Address Input
.CLKA(CLKA), // Port A Clock
.CLKB(CLKB), // Port B Clock
.DIA(DIA), // Port A 16-bit Data Input
.DIB(DIB), // Port B 32-bit Data Input
.DIPA(DIPA), // Port A 2-bit parity Input
.DIPB(DIPB), // Port-B 4-bit parity Input
.ENA(ENA12), // Port A RAM Enable Input
.ENB(ENB12), // PortB RAM Enable Input
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
.WEA(WEA), // Port A Write Enable Input
.WEB(WEB) // Port B Write Enable Input
);
RAMB16_S18_S36 BRAM13 (
.DOA(DOA13), // Port A 16-bit Data Output
.DOB(DOB13), // Port B 32-bit Data Output
.DOPA(DOPA13), // Port A 2-bit Parity Output
.DOPB(DOPB13), // Port B 4-bit Parity Output
.ADDRA(ADDRA[9:0]), // Port A 10-bit Address Input
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