counter16.v

来自「控制两组,每组三个电梯的verilog实现」· Verilog 代码 · 共 40 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:43:24 01/10/07
// Design Name:    
// Module Name:    counter16
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module counter16(timeup,time_stop,clk,reset);
parameter width = 16;
input clk,reset;
input [width-1:0] time_stop;
output timeup;	  reg timeup;

reg [width-1:0] times;

always @ (posedge clk)
begin
if(!reset) 
  begin times<=0; timeup<=0;end
  else 
  begin 
       if (times>= time_stop)  begin timeup<=1; times<=times;end
		  else times <= times +1;
  end
end
endmodule