des_floor.v

控制两组,每组三个电梯的verilog实现

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    09:15:03 12/30/06
// Design Name:    
// Module Name:    des_floor
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module des_floor(des_flo_out,address,set,reset,reset_f,clk);
input reset,reset_f ,set,clk;
input [3:0] address;

output [15:0] des_flo_out;
reg  [15:0] des_flo_out;
reg [3:0]start_j;
reg stay_f;												 
always @ ( posedge clk or negedge reset) 
begin
     stay_f = 0;
     if(!reset)  des_flo_out = 0;
		 else  if(set == 1) 
	    begin
       case (address)
          0:des_flo_out[0] = des_flo_out[0] + 1;
          1:des_flo_out[1] = des_flo_out[1] + 1;
			 2:des_flo_out[2] = des_flo_out[2] + 1;
			 3:des_flo_out[3] = des_flo_out[3] + 1;
			 4:des_flo_out[4] = des_flo_out[4] + 1;
			 5:des_flo_out[5] = des_flo_out[5] + 1;
			 6:des_flo_out[6] = des_flo_out[6] + 1;
			 7:des_flo_out[7] = des_flo_out[7] + 1;
			 8:des_flo_out[8] = des_flo_out[8] + 1;
			 9:des_flo_out[9] = des_flo_out[9] + 1;
			 10:des_flo_out[10] = des_flo_out[10] + 1;
			 11:des_flo_out[11] = des_flo_out[11] + 1;
			 12:des_flo_out[12] = des_flo_out[12] + 1;
			 13:des_flo_out[13] = des_flo_out[13] + 1;
			 14:des_flo_out[14] = des_flo_out[14] + 1;
			 15:des_flo_out[15] = des_flo_out[15] + 1;
		  endcase 
		stay_f=1;
		end
	  else if(start_j == 3 &&reset_f) des_flo_out = 0;
		    
end

always @ (posedge clk or negedge reset)
begin
if( !reset) start_j=0;
else if (stay_f == 1)	start_j=0;
else
  if(start_j<3)	start_j=start_j+1;
  else 	 start_j=start_j;
end

endmodule