datamem.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 50 行

//******************************************************************************
//
// datamem.v
//
// the implementation for data memory.
//
//
//******************************************************************************

module datamem (
	address,
	clock,
	data,
	wren,
	q);

	input	[3:0]  address;
	input	  clock;
	input	[31:0]  data;
	input	  wren;
	output	[31:0]  q;
	reg [31:0] mem [0:15];
	
	initial 
	begin
		mem[0] = 32'h000000A3;
		mem[1] = 32'h00000027;
		mem[2] = 32'h00000079;
		mem[3] = 32'h00000115;
		mem[4] = 32'h00000000;
		mem[5] = 32'h00000000;
		mem[6] = 32'h00000000;
		mem[7] = 32'h00000000;
		mem[8] = 32'h00000000;
		mem[9] = 32'h00000000;
		mem[10] = 32'h00000000;
		mem[11] = 32'h00000000;
		mem[12] = 32'h00000000;
		mem[13] = 32'h00000000;
		mem[14] = 32'h00000000;
		mem[15] = 32'h00000000;
	end
	always @ (posedge clock) 
	begin
		if (wren)
			mem[address] <= data;
	end
	assign q = mem[address];

endmodule