📄 balucaideng.rpt
字号:
- 8 - C 21 DFFE + 1 1 0 1 |74160:2|QD (|74160:2|:9)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\balucaideng\balucaideng.rpt
balucaideng
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\balucaideng\balucaideng.rpt
balucaideng
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: d:\balucaideng\balucaideng.rpt
balucaideng
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information: d:\balucaideng\balucaideng.rpt
balucaideng
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'l1'
-- Equation name is 'l1', type is output
l1 = _LC6_C21;
-- Node name is 'l2'
-- Equation name is 'l2', type is output
l2 = _LC7_C13;
-- Node name is 'l3'
-- Equation name is 'l3', type is output
l3 = _LC5_C13;
-- Node name is 'l4'
-- Equation name is 'l4', type is output
l4 = _LC4_C13;
-- Node name is 'l5'
-- Equation name is 'l5', type is output
l5 = _LC3_C21;
-- Node name is 'l6'
-- Equation name is 'l6', type is output
l6 = _LC1_C13;
-- Node name is 'l7'
-- Equation name is 'l7', type is output
l7 = _LC7_C21;
-- Node name is 'l8'
-- Equation name is 'l8', type is output
l8 = _LC5_C21;
-- Node name is '|74160:2|:6' = '|74160:2|QA'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = DFFE(!_LC2_C21, GLOBAL( clk), clr, VCC, VCC);
-- Node name is '|74160:2|:7' = '|74160:2|QB'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = DFFE( _EQ001, GLOBAL( clk), clr, VCC, VCC);
_EQ001 = _LC1_C21 & !_LC2_C21
# _LC1_C21 & !_LC4_C21 & _LC8_C21
# !_LC1_C21 & _LC2_C21 & !_LC4_C21 & !_LC8_C21;
-- Node name is '|74160:2|:8' = '|74160:2|QC'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = DFFE( _EQ002, GLOBAL( clk), clr, VCC, VCC);
_EQ002 = _LC1_C21 & _LC2_C21 & !_LC4_C21
# !_LC2_C21 & _LC4_C21;
-- Node name is '|74160:2|:9' = '|74160:2|QD'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = DFFE( _EQ003, GLOBAL( clk), clr, VCC, VCC);
_EQ003 = !_LC2_C21 & _LC8_C21;
-- Node name is '~4~1'
-- Equation name is '~4~1', location is LC6_C21, type is buried.
-- synthesized logic cell
_LC6_C21 = LCELL( _EQ004);
_EQ004 = !_LC1_C21 & !_LC2_C21
# !_LC2_C21 & !_LC4_C21;
-- Node name is ':4'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = LCELL( _EQ005);
_EQ005 = !_LC1_C21 & !_LC2_C21
# !_LC2_C21 & !_LC4_C21;
-- Node name is '~5~1'
-- Equation name is '~5~1', location is LC7_C13, type is buried.
-- synthesized logic cell
_LC7_C13 = LCELL( _EQ006);
_EQ006 = !_LC1_C21 & !_LC2_C21
# _LC1_C21 & _LC2_C21 & !_LC4_C21;
-- Node name is ':5'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ007);
_EQ007 = _LC1_C21 & _LC2_C21 & !_LC4_C21
# !_LC1_C21 & !_LC2_C21;
-- Node name is '~7~1'
-- Equation name is '~7~1', location is LC3_C21, type is buried.
-- synthesized logic cell
_LC3_C21 = LCELL( _EQ008);
_EQ008 = !_LC1_C21 & _LC2_C21 & _LC4_C21
# !_LC2_C21 & !_LC4_C21;
-- Node name is ':7'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ009);
_EQ009 = !_LC2_C21 & !_LC4_C21
# !_LC1_C21 & _LC2_C21 & _LC4_C21;
-- Node name is '~29~1'
-- Equation name is '~29~1', location is LC5_C21, type is buried.
-- synthesized logic cell
_LC5_C21 = LCELL( _EQ010);
_EQ010 = !_LC1_C21 & !_LC2_C21 & !_LC4_C21
# _LC1_C21 & _LC2_C21 & !_LC4_C21
# !_LC1_C21 & _LC2_C21 & _LC4_C21;
-- Node name is ':29'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ011);
_EQ011 = _LC1_C21 & _LC2_C21 & !_LC4_C21
# !_LC1_C21 & !_LC2_C21 & !_LC4_C21
# !_LC1_C21 & _LC2_C21 & _LC4_C21;
Project Information d:\balucaideng\balucaideng.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,812K
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