_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity fifo_register000 is
    port(
        clock1          : in     vl_logic;
        clock2          : in     vl_logic;
        shift_fifo      : in     vl_logic;
        hold_fifo       : in     vl_logic;
        en_outfifo      : in     vl_logic;
        en_infifo       : in     vl_logic;
        datain          : in     vl_logic_vector(4 downto 0);
        dataout         : out    vl_logic_vector(4 downto 0)
    );
end fifo_register000;