_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity Delay1 is
    generic(
        width           : integer := 8
    );
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        \in\            : in     vl_logic_vector;
        \out\           : out    vl_logic_vector
    );
end Delay1;