cnt_fry.fnsim.qmsg

本程序功能是由VHDL语言实现对频率的测量

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg\[1\] cnt_fry.vhd(72) " "Info (10041): Inferred latch for \"seg\[1\]\" at cnt_fry.vhd(72)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg\[2\] cnt_fry.vhd(72) " "Info (10041): Inferred latch for \"seg\[2\]\" at cnt_fry.vhd(72)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg\[3\] cnt_fry.vhd(72) " "Info (10041): Inferred latch for \"seg\[3\]\" at cnt_fry.vhd(72)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg\[4\] cnt_fry.vhd(72) " "Info (10041): Inferred latch for \"seg\[4\]\" at cnt_fry.vhd(72)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg\[5\] cnt_fry.vhd(72) " "Info (10041): Inferred latch for \"seg\[5\]\" at cnt_fry.vhd(72)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg\[6\] cnt_fry.vhd(72) " "Info (10041): Inferred latch for \"seg\[6\]\" at cnt_fry.vhd(72)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg\[7\] cnt_fry.vhd(72) " "Info (10041): Inferred latch for \"seg\[7\]\" at cnt_fry.vhd(72)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[0\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"data\[0\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[1\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"data\[1\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[2\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"data\[2\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[3\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"data\[3\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[0\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"scan\[0\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[1\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"scan\[1\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[2\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"scan\[2\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[3\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"scan\[3\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[4\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"scan\[4\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[5\] cnt_fry.vhd(58) " "Info (10041): Inferred latch for \"scan\[5\]\" at cnt_fry.vhd(58)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "flag\[0\] cnt_fry.vhd(31) " "Info (10041): Inferred latch for \"flag\[0\]\" at cnt_fry.vhd(31)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 31 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "flag\[1\] cnt_fry.vhd(31) " "Info (10041): Inferred latch for \"flag\[1\]\" at cnt_fry.vhd(31)" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 31 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "29 " "Info: Inferred 29 megafunctions from design logic" { { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux0\"" {  } { { "cnt_fry.vhd" "Mux0" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "cnt_fry.vhd" "Add0" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 23 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add1\"" {  } { { "cnt_fry.vhd" "Add1" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 24 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux1\"" {  } { { "cnt_fry.vhd" "Mux1" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add2 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add2\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add2" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add3" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux2\"" {  } { { "cnt_fry.vhd" "Mux2" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add4" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add5" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux3\"" {  } { { "cnt_fry.vhd" "Mux3" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add6 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add6\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add6" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux4\"" {  } { { "cnt_fry.vhd" "Mux4" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add7 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add7\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add7" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add8 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add8\"" {  } { { "cnt_fry.vhd" "Add8" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 51 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux5\"" {  } { { "cnt_fry.vhd" "Mux5" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux6\"" {  } { { "cnt_fry.vhd" "Mux6" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux7\"" {  } { { "cnt_fry.vhd" "Mux7" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux8\"" {  } { { "cnt_fry.vhd" "Mux8" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux9 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux9\"" {  } { { "cnt_fry.vhd" "Mux9" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux10 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux10\"" {  } { { "cnt_fry.vhd" "Mux10" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux11 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux11\"" {  } { { "cnt_fry.vhd" "Mux11" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux12 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux12\"" {  } { { "cnt_fry.vhd" "Mux12" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux13 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux13\"" {  } { { "cnt_fry.vhd" "Mux13" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux14 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux14\"" {  } { { "cnt_fry.vhd" "Mux14" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 61 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux15 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux15\"" {  } { { "cnt_fry.vhd" "Mux15" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux16 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux16\"" {  } { { "cnt_fry.vhd" "Mux16" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux17 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux17\"" {  } { { "cnt_fry.vhd" "Mux17" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux18 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux18\"" {  } { { "cnt_fry.vhd" "Mux18" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux19 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux19\"" {  } { { "cnt_fry.vhd" "Mux19" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 74 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}