cnt_fry.map.qmsg

本程序功能是由VHDL语言实现对频率的测量

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 18 14:45:33 2008 " "Info: Processing started: Thu Dec 18 14:45:33 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off cnt_fry -c cnt_fry " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cnt_fry -c cnt_fry" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt_fry.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file cnt_fry.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt_fry-one " "Info: Found design unit 1: cnt_fry-one" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "cnt_fry-one" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt_fry " "Info: Found entity 1: cnt_fry" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "cnt_fry" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data0 cnt_fry.vhd(71) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(71): signal data0 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data1 cnt_fry.vhd(71) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(71): signal data1 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data2 cnt_fry.vhd(71) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(71): signal data2 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data3 cnt_fry.vhd(72) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(72): signal data3 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data4 cnt_fry.vhd(72) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(72): signal data4 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data5 cnt_fry.vhd(72) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(72): signal data5 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cnt6 cnt_fry.vhd(82) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(82): signal cnt6 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data0 cnt_fry.vhd(83) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(83): signal data0 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 83 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data1 cnt_fry.vhd(84) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(84): signal data1 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data2 cnt_fry.vhd(85) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(85): signal data2 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data3 cnt_fry.vhd(86) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(86): signal data3 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data4 cnt_fry.vhd(87) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(87): signal data4 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 87 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data5 cnt_fry.vhd(88) " "Warning: VHDL Process Statement warning at cnt_fry.vhd(88): signal data5 is in statement, but is not in sensitivity list" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 88 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count\[0\]~3 14 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=14) from the following logic: count\[0\]~3" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "count\[0\]~3" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "count\[0\]~4 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: count\[0\]~4" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "count\[0\]~4" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "alt_counter_f10ke" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[0\] GND " "Warning: Pin seg\[0\] stuck at GND" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "162 " "Info: Implemented 162 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "145 " "Info: Implemented 145 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 18 14:45:42 2008 " "Info: Processing ended: Thu Dec 18 14:45:42 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}