cnt_fry.tan.qmsg

本程序功能是由VHDL语言实现对频率的测量

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk0 scan\[2\] cnt6\[0\] 13.100 ns register " "Info: Minimum tco from clock clk0 to destination pin scan\[2\] through register cnt6\[0\] is 13.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 5.400 ns + Shortest register " "Info: + Shortest clock path from clock clk0 to source register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk0 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk0'" {  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { clk0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC1_C21 16 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_C21; Fanout = 16; REG Node = 'clk1khz'" {  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.900 ns" { clk0 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.000 ns) 5.400 ns cnt6\[0\] 3 REG LC3_C21 17 " "Info: 3: + IC(0.600 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC3_C21; Fanout = 17; REG Node = 'cnt6\[0\]'" {  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "0.600 ns" { clk1khz cnt6[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 51.85 % " "Info: Total cell delay = 2.800 ns ( 51.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 48.15 % " "Info: Total interconnect delay = 2.600 ns ( 48.15 % )" {  } {  } 0}  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "5.400 ns" { clk0 clk1khz cnt6[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt6\[0\] 1 REG LC3_C21 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C21; Fanout = 17; REG Node = 'cnt6\[0\]'" {  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { cnt6[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 2.000 ns i~47 2 COMB LC4_C21 1 " "Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC4_C21; Fanout = 1; COMB Node = 'i~47'" {  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.000 ns" { cnt6[0] i~47 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(3.900 ns) 6.800 ns scan\[2\] 3 PIN Pin_81 0 " "Info: 3: + IC(0.900 ns) + CELL(3.900 ns) = 6.800 ns; Loc. = Pin_81; Fanout = 0; PIN Node = 'scan\[2\]'" {  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "4.800 ns" { i~47 scan[2] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns 77.94 % " "Info: Total cell delay = 5.300 ns ( 77.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 22.06 % " "Info: Total interconnect delay = 1.500 ns ( 22.06 % )" {  } {  } 0}  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "6.800 ns" { cnt6[0] i~47 scan[2] } "NODE_NAME" } } }  } 0}  } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "5.400 ns" { clk0 clk1khz cnt6[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "6.800 ns" { cnt6[0] i~47 scan[2] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 18 14:45:57 2008 " "Info: Processing ended: Thu Dec 18 14:45:57 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}