📄 cnt_fry.csf.qmsg
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 18 14:45:55 2008 " "Info: Processing started: Thu Dec 18 14:45:55 2008" { } { } 0} } { } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off cnt_fry -c cnt_fry " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off cnt_fry -c cnt_fry" { } { } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk0 " "Info: Assuming node clk0 is an undefined clock" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 6 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk0" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_RIPPLE_CLK" "clk2hz " "Info: Detected ripple clock clk2hz as buffer" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 30 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2hz" } } } } } 0} { "Info" "ITDB_RIPPLE_CLK" "clk1khz " "Info: Detected ripple clock clk1khz as buffer" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk0 register lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[9\] register clk1khz 62.89 MHz 15.9 ns Internal " "Info: Clock clk0 has Internal fmax of 62.89 MHz between source register lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[9\] and destination register clk1khz (period= 15.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.700 ns + Longest register register " "Info: + Longest register to register delay is 13.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[9\] 1 REG LC3_C11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C11; Fanout = 3; REG Node = 'lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[9\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 3.200 ns i~3816 2 COMB LC1_C10 1 " "Info: 2: + IC(1.800 ns) + CELL(1.400 ns) = 3.200 ns; Loc. = LC1_C10; Fanout = 1; COMB Node = 'i~3816'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.200 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] i~3816 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 4.500 ns i~3820 3 COMB LC2_C10 1 " "Info: 3: + IC(0.000 ns) + CELL(1.300 ns) = 4.500 ns; Loc. = LC2_C10; Fanout = 1; COMB Node = 'i~3820'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "1.300 ns" { i~3816 i~3820 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 8.200 ns i~3799 4 COMB LC8_C11 16 " "Info: 4: + IC(1.800 ns) + CELL(1.900 ns) = 8.200 ns; Loc. = LC8_C11; Fanout = 16; COMB Node = 'i~3799'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.700 ns" { i~3820 i~3799 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.400 ns) 12.100 ns clk1khz~1 5 COMB LC5_C21 1 " "Info: 5: + IC(2.500 ns) + CELL(1.400 ns) = 12.100 ns; Loc. = LC5_C21; Fanout = 1; COMB Node = 'clk1khz~1'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { i~3799 clk1khz~1 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 13.700 ns clk1khz 6 REG LC1_C21 16 " "Info: 6: + IC(0.600 ns) + CELL(1.000 ns) = 13.700 ns; Loc. = LC1_C21; Fanout = 16; REG Node = 'clk1khz'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "1.600 ns" { clk1khz~1 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 51.09 % " "Info: Total cell delay = 7.000 ns ( 51.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns 48.91 % " "Info: Total interconnect delay = 6.700 ns ( 48.91 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "13.700 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] i~3816 i~3820 i~3799 clk1khz~1 clk1khz } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk0 to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk0 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk0'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { clk0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk1khz 2 REG LC1_C21 16 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C21; Fanout = 16; REG Node = 'clk1khz'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.000 ns" { clk0 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk0 clk1khz } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 3.900 ns - Longest register " "Info: - Longest clock path from clock clk0 to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk0 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk0'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { clk0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[9\] 2 REG LC3_C11 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C11; Fanout = 3; REG Node = 'lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[9\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.000 ns" { clk0 lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk0 lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } } } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk0 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk0 lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } } } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "13.700 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] i~3816 i~3820 i~3799 clk1khz~1 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk0 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk0 lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dat0\[0\] register dat5\[3\] 53.76 MHz 18.6 ns Internal " "Info: Clock clk has Internal fmax of 53.76 MHz between source register dat0\[0\] and destination register dat5\[3\] (period= 18.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.400 ns + Longest register register " "Info: + Longest register to register delay is 16.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dat0\[0\] 1 REG LC6_A16 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A16; Fanout = 6; REG Node = 'dat0\[0\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { dat0[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 2.500 ns i~3812 2 COMB LC1_A16 6 " "Info: 2: + IC(0.600 ns) + CELL(1.900 ns) = 2.500 ns; Loc. = LC1_A16; Fanout = 6; COMB Node = 'i~3812'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.500 ns" { dat0[0] i~3812 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 6.300 ns _~3 3 COMB LC4_A13 5 " "Info: 3: + IC(1.900 ns) + CELL(1.900 ns) = 6.300 ns; Loc. = LC4_A13; Fanout = 5; COMB Node = '_~3'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.800 ns" { i~3812 _~3 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 8.300 ns dat3\[3\]~0 4 COMB LC1_A13 5 " "Info: 4: + IC(0.600 ns) + CELL(1.400 ns) = 8.300 ns; Loc. = LC1_A13; Fanout = 5; COMB Node = 'dat3\[3\]~0'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.000 ns" { _~3 dat3[3]~0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.400 ns) 11.600 ns dat4\[3\]~0 5 COMB LC1_A14 5 " "Info: 5: + IC(1.900 ns) + CELL(1.400 ns) = 11.600 ns; Loc. = LC1_A14; Fanout = 5; COMB Node = 'dat4\[3\]~0'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.300 ns" { dat3[3]~0 dat4[3]~0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 14.800 ns dat5\[3\]~0 6 COMB LC6_A15 4 " "Info: 6: + IC(1.800 ns) + CELL(1.400 ns) = 14.800 ns; Loc. = LC6_A15; Fanout = 4; COMB Node = 'dat5\[3\]~0'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.200 ns" { dat4[3]~0 dat5[3]~0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 16.400 ns dat5\[3\] 7 REG LC4_A15 3 " "Info: 7: + IC(0.600 ns) + CELL(1.000 ns) = 16.400 ns; Loc. = LC4_A15; Fanout = 3; REG Node = 'dat5\[3\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "1.600 ns" { dat5[3]~0 dat5[3] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 54.88 % " "Info: Total cell delay = 9.000 ns ( 54.88 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.400 ns 45.12 % " "Info: Total interconnect delay = 7.400 ns ( 45.12 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "16.400 ns" { dat0[0] i~3812 _~3 dat3[3]~0 dat4[3]~0 dat5[3]~0 dat5[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 24 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 24; CLK Node = 'clk'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns dat5\[3\] 2 REG LC4_A15 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_A15; Fanout = 3; REG Node = 'dat5\[3\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.000 ns" { clk dat5[3] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk dat5[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 24 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 24; CLK Node = 'clk'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns dat0\[0\] 2 REG LC6_A16 6 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_A16; Fanout = 6; REG Node = 'dat0\[0\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.000 ns" { clk dat0[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk dat0[0] } "NODE_NAME" } } } } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk dat5[3] } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk dat0[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 43 -1 0 } } } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "16.400 ns" { dat0[0] i~3812 _~3 dat3[3]~0 dat4[3]~0 dat5[3]~0 dat5[3] } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk dat5[3] } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.900 ns" { clk dat0[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk0 seg\[3\] data1\[2\] 37.300 ns register " "Info: tco from clock clk0 to destination pin seg\[3\] through register data1\[2\] is 37.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 13.000 ns + Longest register " "Info: + Longest clock path from clock clk0 to source register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk0 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk0'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { clk0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC1_C21 16 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_C21; Fanout = 16; REG Node = 'clk1khz'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.900 ns" { clk0 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.900 ns) 8.300 ns clk2hz 3 REG LC1_C13 26 " "Info: 3: + IC(2.600 ns) + CELL(0.900 ns) = 8.300 ns; Loc. = LC1_C13; Fanout = 26; REG Node = 'clk2hz'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "3.500 ns" { clk1khz clk2hz } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 13.000 ns data1\[2\] 4 REG LC2_A23 1 " "Info: 4: + IC(4.700 ns) + CELL(0.000 ns) = 13.000 ns; Loc. = LC2_A23; Fanout = 1; REG Node = 'data1\[2\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "4.700 ns" { clk2hz data1[2] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 67 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 28.46 % " "Info: Total cell delay = 3.700 ns ( 28.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.300 ns 71.54 % " "Info: Total interconnect delay = 9.300 ns ( 71.54 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "13.000 ns" { clk0 clk1khz clk2hz data1[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 67 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.400 ns + Longest register pin " "Info: + Longest register to pin delay is 23.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data1\[2\] 1 REG LC2_A23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A23; Fanout = 1; REG Node = 'data1\[2\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { data1[2] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 67 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.900 ns) 4.200 ns data\[2\]~37 2 COMB LC3_A24 1 " "Info: 2: + IC(2.300 ns) + CELL(1.900 ns) = 4.200 ns; Loc. = LC3_A24; Fanout = 1; COMB Node = 'data\[2\]~37'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "4.200 ns" { data1[2] data[2]~37 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 6.700 ns data\[2\]~38 3 COMB LC5_A24 1 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 6.700 ns; Loc. = LC5_A24; Fanout = 1; COMB Node = 'data\[2\]~38'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.500 ns" { data[2]~37 data[2]~38 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 9.200 ns data\[2\]~518 4 COMB LC1_A24 9 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 9.200 ns; Loc. = LC1_A24; Fanout = 9; COMB Node = 'data\[2\]~518'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.500 ns" { data[2]~38 data[2]~518 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.400 ns) 13.600 ns i~3804 5 COMB LC8_A5 1 " "Info: 5: + IC(3.000 ns) + CELL(1.400 ns) = 13.600 ns; Loc. = LC8_A5; Fanout = 1; COMB Node = 'i~3804'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "4.400 ns" { data[2]~518 i~3804 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 17.600 ns i~3818 6 COMB LC1_A7 2 " "Info: 6: + IC(2.700 ns) + CELL(1.300 ns) = 17.600 ns; Loc. = LC1_A7; Fanout = 2; COMB Node = 'i~3818'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "4.000 ns" { i~3804 i~3818 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(3.900 ns) 23.400 ns seg\[3\] 7 PIN Pin_21 0 " "Info: 7: + IC(1.900 ns) + CELL(3.900 ns) = 23.400 ns; Loc. = Pin_21; Fanout = 0; PIN Node = 'seg\[3\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "5.800 ns" { i~3818 seg[3] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.300 ns 52.56 % " "Info: Total cell delay = 12.300 ns ( 52.56 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.100 ns 47.44 % " "Info: Total interconnect delay = 11.100 ns ( 47.44 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "23.400 ns" { data1[2] data[2]~37 data[2]~38 data[2]~518 i~3804 i~3818 seg[3] } "NODE_NAME" } } } } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "13.000 ns" { clk0 clk1khz clk2hz data1[2] } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "23.400 ns" { data1[2] data[2]~37 data[2]~38 data[2]~518 i~3804 i~3818 seg[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk0 scan\[2\] cnt6\[0\] 13.100 ns register " "Info: Minimum tco from clock clk0 to destination pin scan\[2\] through register cnt6\[0\] is 13.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 5.400 ns + Shortest register " "Info: + Shortest clock path from clock clk0 to source register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk0 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk0'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { clk0 } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC1_C21 16 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_C21; Fanout = 16; REG Node = 'clk1khz'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.900 ns" { clk0 clk1khz } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.000 ns) 5.400 ns cnt6\[0\] 3 REG LC3_C21 17 " "Info: 3: + IC(0.600 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC3_C21; Fanout = 17; REG Node = 'cnt6\[0\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "0.600 ns" { clk1khz cnt6[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 77 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 51.85 % " "Info: Total cell delay = 2.800 ns ( 51.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 48.15 % " "Info: Total interconnect delay = 2.600 ns ( 48.15 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "5.400 ns" { clk0 clk1khz cnt6[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 77 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt6\[0\] 1 REG LC3_C21 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C21; Fanout = 17; REG Node = 'cnt6\[0\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "" { cnt6[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 77 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 2.000 ns i~47 2 COMB LC4_C21 1 " "Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC4_C21; Fanout = 1; COMB Node = 'i~47'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "2.000 ns" { cnt6[0] i~47 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(3.900 ns) 6.800 ns scan\[2\] 3 PIN Pin_81 0 " "Info: 3: + IC(0.900 ns) + CELL(3.900 ns) = 6.800 ns; Loc. = Pin_81; Fanout = 0; PIN Node = 'scan\[2\]'" { } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "4.800 ns" { i~47 scan[2] } "NODE_NAME" } } } { "I:/prg/cnt_fry/cnt_fry.vhd" "" "" { Text "I:/prg/cnt_fry/cnt_fry.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns 77.94 % " "Info: Total cell delay = 5.300 ns ( 77.94 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 22.06 % " "Info: Total interconnect delay = 1.500 ns ( 22.06 % )" { } { } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "6.800 ns" { cnt6[0] i~47 scan[2] } "NODE_NAME" } } } } 0} } { { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "5.400 ns" { clk0 clk1khz cnt6[0] } "NODE_NAME" } } } { "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" "" "" { Report "I:/prg/cnt_fry/db/cnt_fry_cmp.qrpt" Compiler "cnt_fry" "UNKNOWN" "V1" "I:/prg/cnt_fry/db/cnt_fry.quartus_db" { Floorplan "" "" "6.800 ns" { cnt6[0] i~47 scan[2] } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 18 14:45:57 2008 " "Info: Processing ended: Thu Dec 18 14:45:57 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 17 s " "Info: Quartus II Full Compilation was successful. 0 errors, 17 warnings" { } { } 0}
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