cnt_fry.vhd.bak

本程序功能是由VHDL语言实现对频率的测量

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt_fry is
 port(clk,rst: in std_logic;
      clk0: in std_logic;
	  seg: out std_logic_vector(7 downto 0);
	  scan:out std_logic_vector(5 downto 0));
end ;
architecture one of cnt_fry is
 signal dat0,dat1,dat2,dat3,dat4,dat5: std_logic_vector(3 downto 0);
-- signal data0,data1,data2,data3,data4,data5: std_logic_vector(3 downto 0);
 signal cnt6:integer range 0 to 5;
 signal flag:integer range 0 to 2;
 signal cnt0:integer range 0 to 999;
 signal cnt:std_logic;
 signal data:std_logic_vector(3 downto 0);
begin

process(clk0)
begin
 if clk0'event and clk0='1' then
    cnt0<=cnt0+1;
    cnt6<=cnt6+1;
    if cnt6=5 then cnt6<=0;end if;
    if cnt0=499 then cnt<= not cnt;cnt0<=0;end if;
 end if;
end process;


process(clk,cnt,rst)
begin
if rst='1' then
   flag<=0;
else
  if cnt='1' then
    if flag=0 then
      if clk'event and clk='1' then
            dat0<=dat0+1;
         if dat0="1010" then dat0<="0000";dat1<=dat1+1;end if;
         if dat1="1010" then dat1<="0000";dat2<=dat2+1;end if;
         if dat2="1010" then dat2<="0000";dat3<=dat3+1;end if;
         if dat3="1010" then dat3<="0000";dat4<=dat4+1;end if;
         if dat4="1010" then dat4<="0000";dat5<=dat5+1;end if;
         if dat5="1010" then dat5<="0000";end if;
      end if;
    end if;
  else if flag=2 then flag<=0;
          dat0<="0000";dat1<="0000";dat2<="0000";
          dat3<="0000";dat4<="0000";dat5<="0000";
       else flag<=flag+1;end if;
  end if;
end if;
end process;



process(cnt6)
begin
case cnt6 is 
     when 0=> scan<="000001"; data<=dat0;
     when 1=> scan<="000010"; data<=dat1;
     when 2=> scan<="000100"; data<=dat2;
     when 3=> scan<="001000"; data<=dat3;
	 when 4=> scan<="010000"; data<=dat4;
	 when 5=> scan<="100000"; data<=dat5;
end case;

end process;
  
process(data)
begin
case data is
     when "0000"=> seg<="11111100";
     when "0001"=> seg<="01100000";
     when "0010"=> seg<="11011010";
     when "0011"=> seg<="11110010";
	 when "0100"=> seg<="01100110";
	 when "0101"=> seg<="10110110";
	 when "0110"=> seg<="10111110";
	 when "0111"=> seg<="11100000";
     when "1000"=> seg<="11111110";
     when "1001"=> seg<="11110110";
     when others=>null;
end case;
end process;
end one;