cnt_fry.vhd

本程序功能是由VHDL语言实现对频率的测量

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt_fry is
 port(clk,rst: in std_logic;
      clk0: in std_logic;
	  seg: out std_logic_vector(7 downto 0);
	  scan:out std_logic_vector(5 downto 0));
end ;
architecture one of cnt_fry is
 signal dat0,dat1,dat2,dat3,dat4,dat5: std_logic_vector(3 downto 0);
 signal data0,data1,data2,data3,data4,data5: std_logic_vector(3 downto 0);
 signal cnt6:integer range 0 to 5;
 signal clk1khz,clk2hz:std_logic;
 signal data:std_logic_vector(3 downto 0);
begin
process(clk0)------------------------------------1KHZ分频
   variable count :integer range 0 to 9999;
begin
   if clk0'event and clk0='1' then 
      if count =9999 then clk1khz<= not clk1khz;count:=0;
      else count:=count+1; 
      end if;
   end if;
end process;

process(clk1khz) ---------------------------------------------0.5HZ 
 variable count:integer range 0 to 999;
begin
  if clk1khz'event and clk1khz='1' then 
      if count =999 then clk2hz<= not clk2hz;count:=0;
      else count:=count+1; 
      end if;
  end if;
end process;
process(clk2hz,clk,rst)
begin
if rst='1' then
   dat0<="0000";dat1<="0000";dat2<="0000";
   dat3<="0000";dat4<="0000";dat5<="0000";
else
  if clk2hz='1' then
      if clk'event and clk='1' then
         if dat0="1010" then dat0<="0000";
           if dat1="1010" then dat1<="0000";
             if dat2="1010" then dat2<="0000";
               if dat3="1010" then dat3<="0000";
                 if dat4="1010" then dat4<="0000";
                   if dat5="1010" then dat5<="0000";
                   else dat5<=dat5+1;end if;
                 else dat4<=dat4+1;end if;
               else dat3<=dat3+1;end if;
             else dat2<=dat2+1;end if;
           else dat1<=dat1+1;end if;
         else dat0<=dat0+1;end if;
      end if;
  else if clk2hz='0' then
          dat0<="0000";dat1<="0000";dat2<="0000";
          dat3<="0000";dat4<="0000";dat5<="0000";
       end if;
  end if;
end if;
end process;

process(clk2hz)
begin
  if clk2hz'event and clk2hz='0' then
     data0<=dat0;data1<=dat1;data2<=dat2;
     data3<=dat3;data4<=dat4;data5<=dat5;
  else 
     data0<=data0;data1<=data1;data2<=data2;
     data3<=data3;data4<=data4;data5<=data5;
  end if;
end process;
process(clk1khz)
begin
   if clk1khz'event and clk1khz='0' then
      if cnt6=5 then cnt6<=0;
      else cnt6<=cnt6+1;
      end if;
   end if;
case cnt6 is 
     when 0=> scan<="000001"; data<=data0;
     when 1=> scan<="000010"; data<=data1;
     when 2=> scan<="000100"; data<=data2;
     when 3=> scan<="001000"; data<=data3;
	 when 4=> scan<="010000"; data<=data4;
	 when 5=> scan<="100000"; data<=data5;
end case;
end process;
  
process(data)
begin
case data is
     when "0000"=> seg<="11111100";
     when "0001"=> seg<="01100000";
     when "0010"=> seg<="11011010";
     when "0011"=> seg<="11110010";
	 when "0100"=> seg<="01100110";
	 when "0101"=> seg<="10110110";
	 when "0110"=> seg<="10111110";
	 when "0111"=> seg<="11100000";
     when "1000"=> seg<="11111110";
     when "1001"=> seg<="11110110";
     when others=>null;
end case;
end process;
end one;