cnt_fry.map.rpt

本程序功能是由VHDL语言实现对频率的测量

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                             ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node             ; Logic Cells ; Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                             ;
+----------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------+
; |cnt_fry                               ; 145 (121)   ; 77        ; 0           ; 17   ; 68 (68)      ; 27 (27)           ; 50 (26)          ; 24 (0)          ; |cnt_fry                                                        ;
;    |lpm_counter:count_rtl_0|           ; 14 (0)      ; 14        ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 14 (0)           ; 14 (0)          ; |cnt_fry|lpm_counter:count_rtl_0                                ;
;       |alt_counter_f10ke:wysi_counter| ; 14 (14)     ; 14        ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 14 (14)          ; 14 (14)         ; |cnt_fry|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter ;
;    |lpm_counter:count_rtl_1|           ; 10 (0)      ; 10        ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 10 (0)           ; 10 (0)          ; |cnt_fry|lpm_counter:count_rtl_1                                ;
;       |alt_counter_f10ke:wysi_counter| ; 10 (10)     ; 10        ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |cnt_fry|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter ;
+----------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------+


+---------------------------------+
; Analysis & Synthesis Equations  ;
+---------------------------------+
The equations can be found in I:/prg/cnt_fry/cnt_fry.map.eqn.


+-----------------------------------------------------------------+
; Analysis & Synthesis Files Read                                 ;
+------------------------------------------------------------------
; File Name                                                ; Read ;
+----------------------------------------------------------+------+
; cnt_fry.vhd                                              ; Read ;
; c:/quartus/libraries/megafunctions/lpm_counter.tdf       ; Read ;
; c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf ; Read ;
+----------------------------------------------------------+------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource                      ; Usage       ;
+-------------------------------+-------------+
; Logic cells                   ; 145         ;
; Total combinational functions ; 118         ;
; Total registers               ; 77          ;
; I/O pins                      ; 17          ;
; Maximum fan-out node          ; clk2hz      ;
; Maximum fan-out               ; 26          ;
; Total fan-out                 ; 503         ;
; Average fan-out               ; 3.10        ;
+-------------------------------+-------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 29    ;
; Number of synthesis-generated cells                    ; 116   ;
; Number of WYSIWYG LUTs                                 ; 29    ;
; Number of synthesis-generated LUTs                     ; 89    ;
; Number of WYSIWYG registers                            ; 24    ;
; Number of synthesis-generated registers                ; 53    ;
; Number of cells with combinational logic only          ; 68    ;
; Number of cells with registers only                    ; 27    ;
; Number of cells with combinational logic and registers ; 50    ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 24    ;
; Number of registers using SLOAD      ; 0     ;
; Number of registers using ACLR       ; 24    ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 22    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Dec 18 14:45:33 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cnt_fry -c cnt_fry
Info: Found 2 design units and 1 entities in source file cnt_fry.vhd
    Info: Found design unit 1: cnt_fry-one
    Info: Found entity 1: cnt_fry
Warning: VHDL Process Statement warning at cnt_fry.vhd(71): signal data0 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(71): signal data1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(71): signal data2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(72): signal data3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(72): signal data4 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(72): signal data5 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(82): signal cnt6 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(83): signal data0 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(84): signal data1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(85): signal data2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(86): signal data3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(87): signal data4 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cnt_fry.vhd(88): signal data5 is in statement, but is not in sensitivity list
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=14) from the following logic: count[0]~3
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: count[0]~4
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Warning: Output pins are stuck at VCC or GND
    Warning: Pin seg[0] stuck at GND
Info: Implemented 162 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 14 output pins
    Info: Implemented 145 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Processing ended: Thu Dec 18 14:45:42 2008
    Info: Elapsed time: 00:00:08