📄 cnt_fry.fit.rpt
字号:
Fitter report for cnt_fry
Thu Dec 18 14:45:49 2008
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Floorplan View
7. Input Pins
8. Output Pins
9. All Package Pins
10. Control Signals
11. Global & Other Fast Signals
12. Carry Chains
13. Cascade Chains
14. Non-Global High Fan-Out Signals
15. Peripheral Signals
16. LAB
17. Local Routing Interconnect
18. LAB External Interconnect
19. Row Interconnect
20. LAB Column Interconnect
21. LAB Column Interconnect
22. Fitter Resource Usage Summary
23. Fitter Resource Utilization by Entity
24. Delay Chain Summary
25. Pin-Out File
26. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------+
; Fitter Status ; Successful - Thu Dec 18 14:45:49 2008 ;
; Revision Name ; cnt_fry ;
; Top-level Entity Name ; cnt_fry ;
; Family ; FLEX10K ;
; Device ; EPF10K10LC84-3 ;
; Total logic elements ; 145 / 576 ( 25 % ) ;
; Total pins ; 17 / 59 ( 28 % ) ;
; Total memory bits ; 0 / 12,288 ( 0 % ) ;
+-----------------------+---------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+-------------------------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+--------------------+--------------------+
; Device ; EPF10K10LC84-3 ; ;
; Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains ; On ; On ;
; Logic Cell Insertion - Individual Logic Cells ; On ; On ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Slow Slew Rate ; Off ; Off ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; FIT_ONLY_ONE_ATTEMPT ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Optimize Timing ; Normal Compilation ; Normal Compilation ;
+------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+--------------------------------------------------------------------------
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error ; On ;
; Release clears before tri-states ; Off ;
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+-------------------+
; Fitter Equations ;
+-------------------+
The equations can be found in I:/prg/cnt_fry/cnt_fry.fit.eqn.
+-----------------+
; Floorplan View ;
+-----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Name ; Pin # ; Row ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; Single-Pin CE ; I/O Standard ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
; clk0 ; 1 ; -- ; -- ; 15 ; yes ; no ; no ; no ; no ; TTL ;
; clk ; 42 ; -- ; -- ; 24 ; yes ; no ; no ; no ; no ; TTL ;
; rst ; 3 ; -- ; 12 ; 1 ; no ; no ; no ; no ; no ; TTL ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Name ; Pin # ; Row ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; Single-Pin OE ; Single-Pin CE ; Open Drain ; I/O Standard ;
+---------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+--------------+
; seg[7] ; 16 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; seg[6] ; 17 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; seg[5] ; 18 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; seg[4] ; 19 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; seg[3] ; 21 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; seg[2] ; 22 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; seg[1] ; 23 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; scan[5] ; 78 ; -- ; 24 ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; scan[4] ; 79 ; -- ; 24 ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; scan[3] ; 80 ; -- ; 23 ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; scan[2] ; 81 ; -- ; 22 ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; scan[1] ; 10 ; -- ; 1 ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; scan[0] ; 11 ; -- ; 1 ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; seg[0] ; 24 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; TTL ;
+---------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+--------------+
+-----------------------------------+
; All Package Pins ;
+------------------------------------
; Pin # ; Usage ; I/O Standard ;
+-------+------------+--------------+
; 1 ; clk0 ; TTL ;
; 2 ; GND+ ; ;
; 3 ; rst ; TTL ;
; 4 ; VCC_INT ; ;
; 5 ; GND* ; ;
; 6 ; GND* ; ;
; 7 ; GND* ; ;
; 8 ; GND* ; ;
; 9 ; GND* ; ;
; 10 ; scan[1] ; TTL ;
; 11 ; scan[0] ; TTL ;
; 12 ; ^DATA0 ; ;
; 13 ; ^DCLK ; ;
; 14 ; ^nCE ; ;
; 15 ; #TDI ; ;
; 16 ; seg[7] ; TTL ;
; 17 ; seg[6] ; TTL ;
; 18 ; seg[5] ; TTL ;
; 19 ; seg[4] ; TTL ;
; 20 ; VCC_INT ; ;
; 21 ; seg[3] ; TTL ;
; 22 ; seg[2] ; TTL ;
; 23 ; seg[1] ; TTL ;
; 24 ; seg[0] ; TTL ;
; 25 ; GND* ; ;
; 26 ; GND_INT ; ;
; 27 ; GND* ; ;
; 28 ; GND* ; ;
; 29 ; GND* ; ;
; 30 ; GND* ; ;
; 31 ; ^MSEL0 ; ;
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